no load worst case for stability?

[analogmind]

Why is no load worst case for stability analysis of opamp?
What happens if we have load resistance and do stability analysis? ( ie break loop and test)
Why should we have load capacitance while doing stability analysis?
Why should we not have load resistance while doing stability analysis?

 

[leo_o2]

Usually, the output node will contribute a non-dominant pole under heavy load. However, this pole will become lower frequency pole when load is reduce to 0A. No load means the resistance is high. RC will be big. To break loop, pls use a big inductor(>10GH).