Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Ideally, it sould not make a difference as long as you keep your MOS well biased (i.e. deep into accumulation). But, still PMOS can be preffered owing to its relatively low process variation which gives you a more defined cap across corners.
When you have a PMOS transistor inside N-Well region your substrate for this transistor is also isolated from substrate of other noisy spaces. This help you when you connect your source terminal to substrate. The other thing is that the NPN transistor (a very weak transistor in the structure of CMOS circuits) does not turned on this way.