Nexys2, ditributed RAM and block RAM

[cyboman]

i have a Nexys2 board and i'm just learning digital design. i'm reading a book about it and it talks about distributed RAM and block RAM. the book explains what it is but i'm still confused. can anyone explain the difference?

help is appreciated
thanks

Added after 42 minutes:

never mind. i figured it out.

 

[research_vlsi]

You are Coding a RAM for some purpose in your design. Depending upon the size of the RAM, synthesis tool will infer Block RAM or Distributed RAM.

Most FPGA boards have dedicated Block RAMs. So if you code a large/big RAM synthesis tool will infer Block RAM.
on other case if you code a small RAM, in FPGA we have CLB(configurable logic blocks) which have LUTs, This forms distributed RAM.

Hope it may help..

 

[cyboman]

research_vlsi,

thanks for the explanation