Newbie question about matching in layout

[safwatonline]

hello,
hello i am newbie in layout and i have few questions:
1- can i mirror current through (W/L=2.8u/1.4u) to a (W/L=4.2/1.4) as they are 3/2 , i.e. is non-integer ratios good , matching is a necessary here. >>> can any one suggest a common centroid allignment
2- is there something bad in using fingure of W<L ? both in layout "matching" and in operation"physical".
3- how can i match a large # of transistors , like 32 by common centroid , can i match every two together then each group of two ....etc.
thnx

 

[elbadry]

Re: matching

-For better matching, you need to have a unit finger width. As long as you do that, there is no problem with non-integer ratios ( but # of fingers has to be integer of course )

It's preferable to have even number of fingers for easier interdigitation.

- I think that there is no problem with W < L .

- Do you mean you have 32 current mirrors for example? or you have 32 fingers to be matched ( of two transistors only )?

 

[safwatonline]

Re: matching

really thnx 4 the help , about the no. of fingers can i for instance make the two mentioned MOS (W/L=2.8u/1.4u) to a (W/L=4.2/1.4) as:
(W/L=2.8u/1.4u)=2 multipliers each of two 0.7 fingers ,,let each muliplier is A
(W/L=4.2/1.4)= 2 multipliers each of three 0.7 fingers, let each multiplier is B

then
A B
B A

will that work as i dont want to break the MOS and i rathur use multipliers to match , btw if i generate the PCELL then faltten it will it still be probably modeled and would it work in LVS ,


about my last question i mean a 32 MOS each consists of multipliers "each multiplier may have fingers".
thnx again
regards,
a.safwat

 

[elbadry]

Re: matching

For the 2.8 and 4.2, you can make it interdigitataed as:

B B A A B | B A A B B

I think that this pattern has a common centroid ( marked by the | )

For the 32 mirrors, I think you need to place the diode connected in the middle. Then try to make this device your common centroid for the rest of the mirrors

If you flatten a PCELL, there is no problem with LVS I think. Why would you need to flatten it anyway?

 

[safwatonline]

matching

thnx again,,,
i was thinking that i have to flatten to make the matching by fingers not by multipliers "is that right, or can i match by fingers without flattening".
btw is the configuration i suggested ok or not? "as i am trying to make the layout as square as possible .

 

[elbadry]

Re: matching

I don't think you need to flatten for matching. To make two interdigitated transistors, just insert a large transistor with # of fingers = sum of number of fingers and connect as you want.

I think that to make a common centroid of the form:

A B
B A

A and B must be equally sized ( I am not quite sure, however )

 

[ramy_maia]

Re: matching

A B
B A
A and B must be equally sized ( I am not quite sure, however )

is this good for current flow
eg.for a diff pair with current mirror load (ie. unbalanced Amp) the current flows from the upper pmos to the nmos then to the gnd
if each of the upper transistor are made of 2 (multiplier) and if we place them as here the current flow will be like this

Vdd
A\ /B
...../\
B / \A
|........|
|........|

is this ok

 

[eng_islam]

Re: matching

I don't think you need to flatten for matching. To make two interdigitated transistors, just insert a large transistor with # of fingers = sum of number of fingers and connect as you want.

how can i put a transistor like u talk about in the simulator to check it in the circuit befor making layout
also is Virtouso XL will understand something like that?

 

[elbadry]

Re: matching

You cannot put such a transistor in schematic of course. It shouldn't be different in performance than simply setting # of fingers = n in the simulator.

Of course the parasitics will be different, but this can only be extracted after layout RCX.

I am sorry I am not familiar with Layout XL. But if you place this manually, you will pass LVS with no problems isA.

Added after 20 minutes:

A B
B A
A and B must be equally sized ( I am not quite sure, however )

is this good for current flow
eg.for a diff pair with current mirror load (ie. unbalanced Amp) the current flows from the upper pmos to the nmos then to the gnd
if each of the upper transistor are made of 2 (multiplier) and if we place them as here the current flow will be like this

Vdd
A\ /B
...../\
B / \A
|........|


|........|

is this ok

I am not sure I get you. But if your design is not a very high frequency one and not a large current one, you should not over-design your layout. This will add more complexity in routing and maybe more area overhead and at the end you may lose performance due to those. Just try to keep things as simple as possible