To work the FPGA as you designed, for all the signals, you must assign initial values. Otherwise, the FPGA assigns 'zero' as the default value to all signals whenever it is powered up.
Once the system is designed and the core is downloaded on to the FPGA board (into non-volatile memory). then we don't use any sysnthesis tools in real time operation. Of course, the synthesis tool make the FPGA design to have the signals with 'zero' initial values.
Regards,
Vishwa
Added after 7 minutes:
Hi BuBEE
You can not set the signals using synthesis tool. You have to assign the values to your signals in your VHDL program.
If you don't specify an initial value, the place-and-route tools normally choose zero.
For Xilinx FPGAs, that is described in the XST User Guide, section Verilog Language Support, subsection Behavioral Verilog Features. VHDL is roughly equivalent.