[SOLVED] [new1] verilog beginner

/* Verilog for cell 'test1{sch}' from library 'testlib' */
/* Created on Thu Dec 08, 2011 18:43:01 */
/* Last revised on Fri Dec 09, 2011 01:01:37 */
/* Written on Fri Dec 09, 2011 01:10:29 by Electric VLSI Design System, version 9.00 */

module test1(A, B, C);
  input [0:2] A;
  output B;
  output C;

  /* user-specified Verilog code */
  wire [0:2] A;
  wire B;
  wire C;
  
assign C=A[0]|A[1];
  assign B=A[0]&A[1];
  
initial
  begin
  A[0:2] <= 3'b011;
  //#10;
  //A[0:2] <= 3'b111;
  //#10;
  //A[0:2] <= 3'b000;

  end
  
initial begin
  $monitor("OR=%b, AND=%b, IN=%b, time=%t\n", B,C,A[0:2]);
  end

endmodule   /* test1 */

/* Verilog for cell 'test1{sch}' from library 'testlib' */
/* Created on Thu Dec 08, 2011 18:43:01 */
/* Last revised on Fri Dec 09, 2011 01:01:37 */
/* Written on Fri Dec 09, 2011 01:10:29 by Electric VLSI Design System, version 9.00 */

module test1(A,B,C);
  input [0:2] A;
  output B;
  output C;

  /* user-specified Verilog code */
  wire [0:2] A;
  wire B;
  wire C;
  
assign C=A[0]|A[1]|A[2];
assign B=A[0]&A[2]&A[1];
  
endmodule   /* test1 */


module tb;

wire [0:2] A;
wire B,C;
test1 UUT(.A(A),.B(B),.C(C));
initial
  begin
A[0:2] <=3'b101;
#10;
A[0:2] <= 3'b111;
#10;
A[0:2] <= 3'b000;
#10;
$finish;
end
  
initial begin
$monitor("OR=%b, AND=%b, IN=%b, time=%t\n", B,C,A);
end
endmodule