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New Xilinx EDK 3.2: product description

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ddr

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NEW Xilinx EDK 3.2

XILINX EXTENDS PROGRAMMABLE SYSTEMS LEADERSHIP WITH NEW
EMBEDDED DEVELOPMENT KIT AND MICROBLAZE SOFT PROCESSOR

Enhancements increase system performance and deliver significant benefits to embedded designers


EMBEDDED SYSTEMS CONFERENCE, SAN FRANCISCO, Calif., April 23, 2003 - Xilinx, Inc. (NASDAQ: XLNX) today announced version 3.2 of its Embedded Development Kit (EDK), offering significant enhancements to the Xilinx MicroBlaze 32-bit soft processor core and embedded design tools supporting both MicroBlaze and the Virtex-II Pro PowerPC. With new capabilities in the MicroBlaze core such as LocalLink interconnect technology, barrel shifter, instruction and data caches, and hardware divider, designers can now significantly increase system performance while reducing cost. Additionally, new embedded tool enhancements include added support for the Solaris Platform, Block Editor View, and extended debug facilities for multi-processor systems. Designers interested in learning more about Xilinx processor solutions should attend Programmable World 2003. For complete program and registration information, visit www.xilinx.com/PW2003.

"Our embedded customers are enthusiastically adopting EDK with MicroBlaze because it eases design development and enables both high performance and low cost embedded processing, " said Per Holmberg, director of Programmable Systems at Xilinx, "With over 20K users of Xilinx soft processor solutions, designers are recognizing the value of flexible partitioning between hardware and software to reduce overall system and development costs."

"The MicroBlaze solution has proven to be far more than a companion microprocessor to our FPGA compute engines. It has become quite an integral part in shaping the way we are solving problems and is helping reduce our engineering costs," said Ricardo Ramos, president and CEO of Interativa Paineis Eletronicos. "Currently, we use the MicroBlaze processor in our 68 billion Color LED display system to manage calibration and setup routines for the video processor module. The ability to easily modify these functions without completely changing the design allows us to offer a cutting edge product."

New MicroBlaze Features

* User-Configurable Caches: The MicroBlaze soft processor includes direct mapped, level one (L1) instruction and data caches that are configurable up to 64 KB. Memory is divided by address to provide 1 GB of cacheable memory space and 3 GB of non-cacheable memory space to significantly reduce instruction execution time and code space.
* LocalLink to Simplify Software to Hardware Implementations: LocalLink offers a 300 MB/sec direct processor interface and point-to-point connection for custom functions and hardware. This high-bandwidth, configurable depth FIFO interface to the CPU is ideal for streaming applications. Each of the 32 input/output LocalLink connection uses SRL16 for the FIFO which consumes only 36 LUTs for a 32-wide, 16-deep FIFO.
* Hardware Debug Module: The MicroBlaze debug module offers JTAG support for multi-processor debug. Debugging options include configurable break points and watch points, non-intrusive debugging, debugging ROM code.
* 32-Bit Barrel Shifter: The 32-bit barrel shifter is particularly advantageous for applications that shift data logical left or right - a normal code style for C programs. Independent of the shift amount or direction, the barrel shifter instructions take only two clock cycles. It can boost shift execution up to 15 times.
* Hardware Divide: Xilinx has implemented a dedicated MicroBlaze instruction with hardware support for divide functions. Users no longer need to run a software library function to perform divides. The hardware divider combined with other enhanced features results in higher processor performance.

The MicroBlaze core delivers unparalleled performance running at 68 Dhrystone-MIPS in the recently announced Spartan-3 FPGA and 125 DMIPS in the Virtex-II Pro FPGA. A typical MicroBlaze system that includes the soft processor core, bus structure, Timer, GPIO and UART peripherals connected to the IBM CoreConnect ™ bus and/or the new LocalLink direct interface consumes less than 5% of the total available logic resources in the 3S1500 Spartan-3 FPGA.

New features in Embedded Design Tools
The new version of the Embedded Development Kit provides embedded designers with an environment to debug hardware and software portions of an embedded system using the MicroBlaze core or the Virtex-II Pro PowerPC. With this enhanced capability, users can leverage a JTAG based on-chip debug which allows non-intrusive control, monitoring of the entire processor system and its associated memory and provides the capability of viewing the signals from the processor interface. Advanced debug capability with the new version of EDK supports hardware break-points and address and data watch points in processor systems that use multiple PowerPC or MicroBlaze cores, as well as a combination of MicroBlaze and PowerPC cores. With the new debug capabilities, embedded designers can now complete system verification both in hardware and simulation, cutting down dramatically on the debug time and improving time to market. Block Diagram View is another new EDK capability that allows users to define and generate a FPGA-based embedded system. With this new feature, users can simply define and generate an embedded system according to their specification with little intervention, streamlining design complexity and freeing resources for other tasks.
 

haifengyuyun

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has any tutorial file for it?

has any tutorial file for it?
 

allegro

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Do we need it?
 

Jayson

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Would it be possible to presume that you folks talking about tutorials for this, already have version 3.2? I so I was wondering if you could share with the rest of us?

- Jayson
 

nattawoot_s

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What are difference with the current version?
 

Jayson

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For one thing, the new 3.2 will only work with ISE 5.2.

- Jayson
 

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