dainis
Advanced Member level 4
ubicom scenix
h**p://w*w.ubicom.com/products/ip3000/ip3000_processors.html
h**p://w*w.ubicom.com/pdfs/products/ip3000/processor/IP3K-DTB-3023-101.pdf
The IP3023 has been designed from the ground up for the unique requirements of wireless networking and packet processing. Unique techniques such as eight-way multithreading, zero-cycle context switching and a memory-to-memory architecture deliver the necessary performance, reduced cost and size required by wireless applications.
Eight-way multithreading allows the device to effectively operate as eight separate processors, where each thread can be assigned a variable speed from 0 - 250 MHz in 3.9 MHz increments. As many as six threads can be dedicated to software I/O. In addition, because packet processing doesn't require ongoing access to data by the CPU, on-chip caching isn't necessary. The use of a memory-to-memory architecture allows packets to be processed directly in on-chip memory, eliminating the need for caches, and avoiding cache misses which reduce performance. Memory-to-memory also eliminates the costly silicon needed for caches and off-chip memory.
These capabilities allow the IP3023 to deliver wire-speed performance in one-fourth the silicon area and requires only 10 percent of the off-chip memory employed by traditional architectures. This leads to a lower overall bill of materials (BOM) for designs based on the IP3023.
h**p://w*w.ubicom.com/products/ip3000/ip3000_processors.html
h**p://w*w.ubicom.com/pdfs/products/ip3000/processor/IP3K-DTB-3023-101.pdf
The IP3023 has been designed from the ground up for the unique requirements of wireless networking and packet processing. Unique techniques such as eight-way multithreading, zero-cycle context switching and a memory-to-memory architecture deliver the necessary performance, reduced cost and size required by wireless applications.
Eight-way multithreading allows the device to effectively operate as eight separate processors, where each thread can be assigned a variable speed from 0 - 250 MHz in 3.9 MHz increments. As many as six threads can be dedicated to software I/O. In addition, because packet processing doesn't require ongoing access to data by the CPU, on-chip caching isn't necessary. The use of a memory-to-memory architecture allows packets to be processed directly in on-chip memory, eliminating the need for caches, and avoiding cache misses which reduce performance. Memory-to-memory also eliminates the costly silicon needed for caches and off-chip memory.
These capabilities allow the IP3023 to deliver wire-speed performance in one-fourth the silicon area and requires only 10 percent of the off-chip memory employed by traditional architectures. This leads to a lower overall bill of materials (BOM) for designs based on the IP3023.
