New to VHDL. Question about WAIT FOR (ns), AFTER (ns) statements.

[BlackHelicopter]

Hi,

I'm going through "Learning VHDL by example" and the author is using statements like:

c <= a AND b AFTER 10 ns;
and also...
WAIT FOR 10 ns;

Now when I actually program this in VHDL and then compile and simulate the code in Quartus, these time delays don't show up at my output waveform... Why? What is the statement "AFTER 10ns" actually doing? How does the FPGA know how long 10ns is and why isn't my simulator simulating it?
Also why would the author write that in the book if it doesn't actually do anything in real life? I wish the author would explain it better.

Thank you!

 

[TrickyDicky]

They are for behavioural modelling. Not for actual synthesis. If your simulator is not simulating them, Im assuming you're simulating a synthesised design, rather than the code itself?

 

[Dave_PL]

IMO there is no way that simulator could simulate synthesized design since the code is not synthesizable itself.

You can try use "transport" (if changes of a/b are shorter than 10ns).

 

[TrickyDicky]

IMO there is no way that simulator could simulate synthesized design since the code is not synthesizable itself.

You can try use "transport" (if changes of a/b are shorter than 10ns).

No. This code will work for any RTL simulation. Transport is just another component of a signal assignment that is also no synthesisable!

 

[Dave_PL]

Yeah i know it will work for simulation and simulation only and I gave the idea with the transport because I could have misunderstand the OP. I thought that he sees no changes on signal c so I figured out that changes on a and b were to short.

 

[alexan_e]

These delays can be used only in simulation but i find them very useful when i create a test bench to check the functionality of a vhdl code.

--you can wait for a clock edge like this

wait until rising_edge(clk);  
wait until falling_edge(clk);

-- you can create a clock (the example below has a period of 20ns=50MHz)

clk_process :process
	begin
		for Z in 1 to 1200000
		loop
			clk  <= '1'  ;
			wait for 10 ns;
			clk  <= '0'  ;
			wait for 10 ns;
		end  loop;
		wait;
	end process;

If you have a ram controller in vhdl which reads/writes to a ram chip you can simulate the behavior of the chip using delays in your test bench.

--if you have a ram then in the test bench you can

wait until OE='1';    -- wait until output enable
wait for 10 ns;       -- ram data output delay
data_lines<="00001111"   -- give some value to the data lines
wait until OE='0';     --wait until output enable is 0
wait for 10 ns;       -- ram data output disable delay
data_lines<=(others =>'Z');   -- set all data lines to Z

Alex