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First thing you need to learn is setup and hold time of FF .
And then you can proceed with the method when you connect the two flops and then add the combo logic b/w the flops what are the delays associated with it.
There are so many online tutorials and synopsys Solvnet user guides , go through it and you should be good to go ..
Surely , you need to know some basics about the following topics :
Karnaugh maps and realization of digital circuits
constructing truth tables
Combinational and sequential circuits
timing analysis and set-up/hold timing requirements
then have a look on one of the tutorials available online and make sure you get the following :
how to define your technology files needed for synthesis
how to define your design files
how to define your design constraints especially clock period
how to write output files and reports
start with simple examples then complicate it over and over
LEC is logical equivalence checking between the RTL and synthesized netlist . Functional verification will be done @ the RTL level and to run all the verification on the gate level netlist it will take more simulator time . Hence LEC is required to compare the logical equivalence between RTL and synthesized netlist ..