Leonid_Nidekker
Newbie level 3
Hi all!
I have some problem with my project during simulation in NCLaunch.
When I perform step 'elaboration', following error is appear.
This error likely associated with some construction in my testbanch.
Can anyone help me with this error.
Thanks.
I have some problem with my project during simulation in NCLaunch.
When I perform step 'elaboration', following error is appear.
Code Verilog - [expand] 1 2 3 always_ff @(negedge work) | ncelab: *E,MULAXX (../hdl/tb.sv,222|8): Multiple drivers to always_ff output variable SVIP_D1 detected.
This error likely associated with some construction in my testbanch.
Can anyone help me with this error.
Thanks.
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