Negative setup and hold time?

[useless_skew]

How can a setup/hold time be negative? Please explain.

Thanks

 

[master_picengineer]

It is according to Clock skew and/or Delays in interconnects.

 

[rberek]

This has been discussed previously



r.b.

 

[csmode]

-ve setup/hold will be there in cell library while design,
b'use those r designed with adding some delay(by delay cell) in clock path, so this will cause some delay in clk path,so thats why they add -ve setup time in library for analysis, reverce is for hold.
i think u got the point.

 

[zorro]

Look at this:

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Regards

Z