Negative setup and hold multicycle paths

[hemal]

Hi,

Does anyone know if negative setup or hold multicycle paths exist in design?

If yes then why?

Regards,
Hemal

 

[dolematin]

Hi,

Does anyone know if negative setup or hold multicycle paths exist in design?

If yes then why?

Regards,
Hemal

It means that the design has clouds that have delays with small cycles. For those clouds if cycles > delays --> It will work ok, but cycles < delays --> cause multiclycle paths.

 

[hemal]

Hi,
can you be more specific?
I know multicycle paths exist in case where the path delay is larger than single clock period.
but that will be with positive multicycle override.
My question is about negative multicycle paths.
--Hemal

 

[shelby]

If have seen designs where data launched from a flop needs to arrive at the receiving flop before the same clock edge (not sure what the logic was or why). This translates into a set_multicycle of 0 in the constraints.

 

[eminem_v]

I think there is no meaning in having negative multicycle path .. Correct me if am wrong...

 

[jmarcelold]

Considering the case of two registers connected sequentially. Both have the same clock signal. Both receive an periodic enable signal active in one in every four clock cycles, but the enable signal of one register is delayed by two cycle in relation of the enable signal of the other register. According to my understanding you can set a negative multicycle hold of two clock and a positive multicycle setup of two cycle for this path. Please, someone correct me if I am wrong.

 

[vijay.mani884]

Hello all,

In some cases the combo logic data path can take more than one cycle to propagate through the logic. by defualt the PT tool assumes that the lauch and capture hap at the launch and capture edge respectively but in this case we direct the tool to pick the relevant capture edge as per the MCP declarations. Usually, as per my experience, this condition comes whenever you find a "MULTIPLIER logic in your design". Since, it usually take more than one clock cycle to propate through it.

Now, if a multicycle setup of "N(cycles)" is specified then we must specified a multicycle hold of "N-1(cycles)". If we miss this then you will find a violation. I hope this is clear.

Now coming to your questions aabout MCP (negative). This usually hap at single cycle data-to-data checks. In this case, setup is checked at 0 time units thus hold will shift to -1. This type of check is usually done while analysing interfaces. ususlly done between two data pins.

For my info kindly refer, PTUGF

 

[jmarcelold]

vijay.mani884,
I do not understand why a multicycle hold must be dependent on multicycle setup. Shouldn't a multicycle hold be set only when the conditions for hold violation changes? For example, in case of an interface where output register and input register has same clock, but not aligned periodic enable signals.

 

[vijay.mani884]

Think about it, supposing you have defined a MCP setup of 3, in your design. Now, by default(means when there is no specification for hold), the tool will check for the hold at edge prior to the setup i.e 3 here in the example, Which is not our intention. We want to capture the data which is launched 2 cycles before .. Since, the actual data which need to be captured is delayed because of the combo logic which is connected in between the launch and capture flops. Thus, its is dependent of setup. There is a concept of "steup dependant hold". this concept is used here. I dont know whether you are aware of this concept or not. Anyways, i feel this will help you..

Cheers.

 

[jmarcelold]

Vijay, I actually got very confused now. In most of the MCS cases, the launch register and capture register has the same enable and clock signal. Thus, hold requirement must be keep unchanged. If I understood correctly, you said that the default behavior of synthesizer is to automatically increase hold time violation by MCS-1 cycles. I think that, this can force the synthesizer to add unnecessarily logic to increase propagation time without need. I have to verify this.

Regards.

Think about it, supposing you have defined a MCP setup of 3, in your design. Now, by default(means when there is no specification for hold), the tool will check for the hold at edge prior to the setup i.e 3 here in the example, Which is not our intention. We want to capture the data which is launched 2 cycles before .. Since, the actual data which need to be captured is delayed because of the combo logic which is connected in between the launch and capture flops. Thus, its is dependent of setup. There is a concept of "steup dependant hold". this concept is used here. I dont know whether you are aware of this concept or not. Anyways, i feel this will help you..

Cheers.

 

[vijay.mani884]

Vijay, I actually got very confused now. In most of the MCS cases, the launch register and capture register has the same enable and clock signal. Thus, hold requirement must be keep unchanged. If I understood correctly, you said that the default behavior of synthesizer is to automatically increase hold time violation by MCS-1 cycles. I think that, this can force the synthesizer to add unnecessarily logic to increase propagation time without need. I have to verify this.

Regards.

Nope, the default behaviour of PT tool is to check hold one clock cycle prior the setup check. Well, i never mentioned about hold violation. Alright, the best to you understand this concept is. First of all draw teo flops namely launch and capture, then add a combo logic in between them, Then draw the waveforms, you will undertand it by youself. remember the best way to understand timing is to draw the waveform and realize the behaviour.

Cheers