Negative HOLD or SETUP timingcheck in SDF file

[sisari]

I am newbie in ASIC design and want to ask what does a negative setup
or hold timecheck in an DC generated SDF file means. I need some help
in understanding the SDF for sequencial components.

 

[mami_hacky]

I do not know any thing about a negative setup time, But negative hold time can be completely natural. Suppose that you are designing a circuit using SSTL2 I/O signaling standard. Simply you will find that the hold time for I/O circuits is negative. What is the reason? And what does it mean? a negative hold time, means that you can change the data on the input pad of your ASIC/FPGA before I/O register's (neg or pos) clock edge. I think a simple picture will describe this well.
Negative hold time is the result of I/O circuit design, have a look at DDR SDRAM datasheets to find out more about it.

Any thing wrong in the above text?

 

[albertyin]

In general, the setup/hold time is positive. But, to help the design, we often design negative hold time for flip/flop, memory and so on, then designer only has to fix setup time violation.
In your SDF, there ofter are negatve timing.
Let me has an example, when the input signal of one buffer has big transition, the output signal of the buffer will has much small transition. As DC is using 1/2 vdd as switching point, but actually not, it somehow likes that the output signal is before input signal, then negative timing appears.

 

[AlexWan]

Let me has an example, when the input signal of one buffer has big transition, the output signal of the buffer will has much small transition. As DC is using 1/2 vdd as switching point, but actually not, it somehow likes that the output signal is before input signal, then negative timing appears.

Thank you for your explain.
How to reduce , even prevent the negative timing appearing? modify the constraints or other ways ?

 

[gerade]

negative hold time,
it is simply that the transition time of the siganl going to be capture is so short, it changes just before you store it in the register.

read book from Rabaey

 

[Monkey]

Negative Setup time can be solved by slowing down your clock or applying tightter cycle constraints during synthesis.
Negtive hold time can be sovled by properly arrange your clock. For example, design an low skew clock or route clock traces opposite the signal propagation direction.