Hi, everybody!
Does anyone have tips for floorplanning memories?
I have a circuit with 16 blocks of memory IP, and I'm doing the floorplanning of this type of circuits for the first time. I know that the pins of the block are in one side.
I don't know what is best place to put the memories.
I attached the last layout I tested. The problem is that i needed lots of optimize steps (adding buffers or upsizing the cells) to clear all negative slacks paths. In the end this will be reflected in the power/area consumption, routing congestion, etc.
My question is:
Is it better to put all memory blocks together and put the std cells in a close area or put the memories like in the figure attached and let the std cells be placed mixed with the memories?
Thanks,
Jorge