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Needed Info on Self Gating ?

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pavanks

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Anyone know about self gating ? It is a low power technique ?
I need some information on this.
If u have any material it would be good.

Thanks
 

oratie

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With the XOR self-gating technique, an XOR gate compares the data stored in the register with the data arriving at the data pin of the register, and the XOR output controls the enable condition for gating.

The XOR self-gating technique turns off the clock signal during specific clock cycles when the data in the register remains unchanged.

To minimize the area and power overhead, an XOR self-gating cell can be shared across a few registers, by creating a combined enable condition with a tree of XOR gates. If the self-gated registers are driven by synchronous set or synchronous clear signals, such signals are also included in the construction of the enable signal so that the circuit remains functionally unchanged.
 

pavanks

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With the XOR self-gating technique, an XOR gate compares the data stored in the register with the data arriving at the data pin of the register, and the XOR output controls the enable condition for gating.

The XOR self-gating technique turns off the clock signal during specific clock cycles when the data in the register remains unchanged.

To minimize the area and power overhead, an XOR self-gating cell can be shared across a few registers, by creating a combined enable condition with a tree of XOR gates. If the self-gated registers are driven by synchronous set or synchronous clear signals, such signals are also included in the construction of the enable signal so that the circuit remains functionally unchanged.

Can u give me a diagram here describing the same ?

Thanks
 

oratie

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41_1318236448.gif
 

pavanks

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Thanks for the fig. Will the output of the ex or gate here will be the enable of the clock gating cell ?
 

oratie

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Yes, xor-cell generates enable for the gating cell.
 

shobhit

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That was good information.

Need to know that does tool (Design Compiler) follow this technique to insert clock gates for power saving , or do we need to guide the tool in a special way to perform gating in this way ?
 

oratie

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You need to guide the tool to perform such kind of gating (compile_ultra -sef_gating, if I remember correctly)
 

shobhit

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The command is compile -gate_clock.................
But my question was that when we give this command to DC does it insert clock gates in the way you explained?

Or to be more clear... are there any other ways in which DC identifies/creates the gating signal of clock gate to be inserted (I thought self gating is one of the ways)
 

oratie

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The option -gate_clock is for ordinary clock-gating insertion. DC inferred from RTL the registers, where it's possible to insert this clock-gating. This option applied to both commands compile and compile_ultra.

The option -selg_gating is additional option for compile_ultra command only. If this option is on, DC may insert self-gating cells on registers only in case, they are not under ordinary clock-gating (so you can use -gate_clock and -self_gating together, -gate_clock has higher priority). Nothing specially for self_gating is required in RTL (for gate_clock RTL must contains special statement like 'if (EN) ...').
 

shitansh

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Here one question, how clock will be enabled again, since once enable pin is activated (o/p of xor), then it will enable pin of gated clock and enable pin of gated cell (o/p of xor gate) will be activated, how to make enable deactivated again with this circuit so that clock will again propagate?????
 

oratie

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Seems, here is misunderstanding. During self-gating, the tool insert XOR-cell plus CG-cell together, and this pair of cells is inserted ONLY for those registers, which have not (inserted before) yet just CG cells. If register already has CG-cell, self-gating is not applied for this register.

Regarding this picture, clock will propagated again in case of different states on D and Q pins.
 

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