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need VHDL code for 16 bit BCD counter

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hasitri

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16 bit counter vhdl

can any body help me........................
 

nand_gates

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6 bit bcd code

Here is verilog code for 16 bit bcd up counter translate this to VHDL!
Hope this helps!

Code:
module bcd_count (
   // Outputs
   count, 
   // Inputs
   clk, reset_n
   );
   input clk, reset_n;
   output [15:0] count;
   reg [15:0] count;
   always @(posedge clk or negedge reset_n) begin
      if (!reset_n) begin
         count <= 0;
      end else begin
         if (count[3:0] == 9) begin
            count[3:0] <= 0;
            if (count[7:4] == 9) begin
               count[7:4] <= 0;
               if (count[11:8] == 9) begin
                  count[11:8] <= 0;
                  if (count[15:12] == 9) begin
                     count[15:12] <= 0;
                  end else begin
                     count[15:12] <= count[15:12] + 1; 
                  end
               end else begin
                  count[11:8] <= count[11:8] + 1;
               end
            end else begin
               count[7:4] <= count[7:4] + 1;
            end   
         end else begin
            count[3:0] <= count[3:0] + 1;
         end
      end
   end
endmodule // bcd_count
 

    hasitri

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wiztronix

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vhdl 16 bit counter

where can i lay my grubby paws on a verilog to vhdl cross compiler? (if that;s what it is called..)

also can someone tell me if i can get a free c to vhdl crosscompiler/convertor??

regards,
wiztronix
 

buark

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bcd to 16 bit

You can not convert c to vhdl, dont try and think about it
respect vhdl
 

hasitri

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vhdl code for bcd counter

frns......
i converted the code into VHDL. but couldnt compile because of errors
the errors are

Error (10500): VHDL syntax error at BCD_16.vhd(14) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at BCD_16.vhd(15) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at BCD_16.vhd(15) near text "then"; expecting "<="
Error (10500): VHDL syntax error at BCD_16.vhd(16) near text "="; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at BCD_16.vhd(17) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at BCD_16.vhd(17) near text "="; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at BCD_16.vhd(18) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at BCD_16.vhd(18) near text "="; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at BCD_16.vhd(19) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at BCD_16.vhd(19) near text "="; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at BCD_16.vhd(20) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at BCD_16.vhd(21) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at BCD_16.vhd(23) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at BCD_16.vhd(25) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at BCD_16.vhd(27) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"






here's the code:
anybody help me in analyzing the errors.


library ieee;
use ieee.std_logic_1164.all;

entity bcd_16 is
port(
clk, reset : in std_logic;
count : out std_logic_vector (15 downto 0)
);
end bcd_16;

architecture counter of bcd_16 is
begin

if reset = '1' then count <= ( others => 0);
elsif ( clk'event and clk = '1') then
if count ( 3 downto 0) = "1001" then count(3 downto 0) <= "0000";
if count ( 7 downto 4) = "1001" then count(7 downto 4) <= "0000";
if count ( 11 downto 8 ) = "1001" then count(11 downto 8 ) <= "0000";
if count ( 15 downto 12) = "1001" then count(15 downto 12) <= "0000";
else count(15 downto 12) <= count(15 downto 12) + '1';
end if;
else count(11 downto 8 ) <= count(11 downto 8 ) + '1';
end if;
else count(11 downto 8 ) <= count(11 downto 8 ) + '1';
end if;
else count(3 downto 0 ) <= count(3 downto 0 ) + '1';
end if;
end if;

end counter;
 

nand_gates

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bcd counter vhdl

Here it goes!
Checkout this!

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bcd_16 is
  port(
    clk, reset : in  std_logic;
    count      : buffer std_logic_vector (15 downto 0)
    );
end bcd_16;

architecture counter of bcd_16 is
begin
bcd_counting: process (clk, reset)
begin  -- process bcd_counting
  if reset = '1' then                   -- asynchronous reset (active high)
    count <= ( others => '0');
  elsif clk'event and clk = '1' then    -- rising clock edge
    if count ( 3 downto 0) = "1001" then
      count(3 downto 0) <= "0000";
      if count ( 7 downto 4) = "1001" then
        count(7 downto 4)  <= "0000";
        if count ( 11 downto 8 ) = "1001" then
          count(11 downto 8 )  <= "0000";
          if count ( 15 downto 12) = "1001" then
            count(15 downto 12) <= "0000";
          else
            count(15 downto 12) <= count(15 downto 12) + '1';
          end if;
        else
          count(11 downto 8 ) <= count(11 downto 8 ) + '1';
        end if;
      else
        count(11 downto 8 ) <= count(11 downto 8 ) + '1';
      end if;
    else
      count(3 downto 0 ) <= count(3 downto 0 ) + '1';
    end if;
  end if;
end process bcd_counting;
end counter;
 
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    hasitri

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    Tero

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hasitri

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16 bit program counter .hdl

thanks again nand_gates

can u tell me why the code gives error widout process statement?
 

nand_gates

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vhd 16bit counter

if then else end if statement is sequential statement only valid in process
construct. Thats why you were getting the errors!
 

hasitri

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16 bit counter implementation in fpga

yeah thanks i got that point.
 

wiztronix

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vhdl syntax error near text )

hey buark,

i think you would do good to check this out regarding C and VHDL

https://www.impulsec.com/


also no offence mean bro, but i dont quite agree in principle to the statement
"respect VHDL"

i mean whats there to respect?? its just another tool like C or Assembly language for that matter.. whats to be respected is the concept of programming or the finesse of implementation.. dont ya think so?

regards,
wiztronix
 

emilliano

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Thank you very much Nand Gates
You have saved my project research, because I have tried create BCD counter 64 Bit, it can run successfully (using combination binary counter and comparator bcd) but It can't reset successfully.
After I run with your program It can run successfully.
Thank you very much.

I will give you my modification program BCD Counter 16 Bit can reset and run with Xilinx ISE XST and Xilinx ISE Simulator successfully.

Best Regards,

Emilliano
PhD with RA
Malaysia

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:46:02 12/24/2009
-- Design Name:
-- Module Name: emil_36c - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity emil_36c is
port(
clk, reset : in std_logic;
bcd1 : out std_logic_vector (3 downto 0);
bcd2 : out std_logic_vector (3 downto 0);
bcd3 : out std_logic_vector (3 downto 0);
bcd4 : out std_logic_vector (3 downto 0));
end emil_36c;

architecture Behavioral of emil_36c is
signal bcd1_int : std_logic_vector (3 downto 0) := "0000";
signal bcd2_int : std_logic_vector (3 downto 0) := "0000";
signal bcd3_int : std_logic_vector (3 downto 0) := "0000";
signal bcd4_int : std_logic_vector (3 downto 0) := "0000";
begin

process (clk, reset)
begin -- process bcd_counting
if reset = '1' then -- asynchronous reset (active high)
bcd1_int <= ( others => '0');
bcd2_int <= ( others => '0');
bcd3_int <= ( others => '0');
bcd4_int <= ( others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if bcd1_int = "1001" then
bcd1_int <= "0000";
if bcd2_int = "1001" then
bcd2_int <= "0000";
if bcd3_int = "1001" then
bcd3_int <= "0000";
if bcd4_int = "1001" then
bcd4_int <= "0000";
else
bcd4_int <= bcd4_int + '1';
end if;
else
bcd3_int <= bcd3_int + '1';
end if;
else
bcd2_int <= bcd2_int + '1';
end if;
else
bcd1_int <= bcd1_int + '1';
end if;
end if;
end process;

bcd1 <= bcd1_int;
bcd2 <= bcd2_int;
bcd3 <= bcd3_int;
bcd4 <= bcd4_int;

end Behavioral;
 

Vinch Singh

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Hey, Could someone please post me how to write 5bit Up/Down Counter with reset and preset in VHDL?

I was blur because of the usage of preset.. Thanks
 

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