Need verilog sample code for interfacing ADC (ADS8556) with fpga V5.

[sid_PESIT]

Hellow,

I am working on a project which includes ADC interfacing FPGA. I have very little idea about it. Please provide a sample code in verilog, which can help.

Thank you!!

 

[sureshaa]

Please go through this doc.**broken link removed**
It is having sample code and documentation and simulation outputs also.Hope it will useful to you.

 

[sid_PESIT]

Please go through this doc.**broken link removed**
It is having sample code and documentation and simulation outputs also.Hope it will useful to you.

Thank you for the reply sureshaa. But i have already went through that document and it only speaks about serial inteface.

I need to go with 16 channel, simultaneous sampling, parallel ADC interface.

Any other suggestions??


Regards,
Sid

 

[sureshaa]

There wont be any different in serial interface and parallel interface of ADC.
If you developed for one channel it can be repeated for 16 channel. Upto my knowledge there wont be any difference for each channel.
If it is yes please share the data sheet.
Things has to taken care while design ADC interface are sample rate and sampling frequency and Format of data(which is available in datasheet).
When I go through the datasheet, I come to know f = 36 Mhz to 100 Khz. And 6 channnel, 16,14,12 bit support.
So Write a one FSM which is operation on any freq within range and send the 16 or 14 or 12 bit data to all 6 channel. That is enough.And Take care of CS, reset timing.