need urgent solution today, requesting all the seniors to please provide solution

[ranveer247]

i want to interface lcd display and display WELCOME INSTEAD OF MECHATRONICS.
But after checking syntex its showng syntex error!


Compiling vhdl file c:/xilinx/bin/lcdint/lcdinterface.vhd in Library work.
ERROR:HDLParsers:164 - c:/xilinx/bin/lcdint/lcdinterface.vhd Line 24. parse error, unexpected SIGNAL
ERROR: XST failed
Process "Check Syntax" did not complete.

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity test_lcd_mod is
port(   CLK_4M          : in STD_LOGIC;  -- 4 Mhz
        RESET               : in STD_LOGIC;
        LCD_D           : out STD_LOGIC_VECTOR (7 downto 0);
        LCD_RW          : out STD_LOGIC;
        LCD_RS          : out STD_LOGIC;
        LCD_E           : out STD_LOGIC ;
          posedge_clk       : out std_logic      
   ); 
end test_lcd_mod;
 
architecture Behavioral of test_lcd_mod is
 -- ****************************************************************************************************************
 
 -- signal  
signal data_s,data_s1 : std_logic_vector(9 downto 0);
signal edge1 : std_logic_vector(1 downto 0);
signal refresh,refresh_d,refresh_s : std_logic;
signal en1,en2 : std_logic;
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_clk : std_logic;--152 Hz
signal lcd_posedge_s : std_logic;-- pose edge of 152 Hz
signal Div : std_logic_vector(10 downto 0);
type state is (wait_state1,func_set0,func_set0_t,func_set0_t1,func_set0_t2,func_set1,func_set1_t,func_set2,func_set2_t,func_set3,func_set3_t,
                    disp_ctrl,disp_ctrl_t,clear_disp,clear_disp_t, mode_set,mode_set_t,cur_set,cur_set_t,ddram_add,ddram_add_t );
signal ps_1, ns_1 : state; 
 
type state1 is (wait_state2,idle1,idle,M,E,C,H,A,T,R,O,N,I,C1,S);
signal prst, nxt : state1;
 
begin
-- Note this design works with a clock of 4M for any other clock plaese modify suitably
 
-----------LCD CLOCK GENERATION(152 HZ)--------------------------------
process(RESET, CLK_4M,Div)
begin
 if( RESET = '1' )then 
    Div <= (others=>'0');
  elsif(CLK_4M'event and CLK_4M = '1')then          
    Div <= Div + 1;  
 end if;
end process;
lcd_clk <= Div(10);
en2 <= Div(10);
 
-- ** Generate a pulse of 4M width on postive edge of LCD_Clock. starts here
process(RESET,CLK_4M,lcd_clk)
begin
    if RESET = '1' then
        edge1 <= "00";
    elsif (CLK_4M'event and CLK_4M = '0') then
        edge1(0)<= lcd_clk;
        edge1(1)<= edge1(0); 
    end if;
end process;
 
lcd_posedge_s <= ((not edge1(1)) and edge1(0));
posedge_clk <= lcd_posedge_s;
-- ** Generate a pulse of 4M width on postive edge of LCD_Clock. ends here
 
--lcd_clk_led <= lcd_posedge_s;
 
--********This FSM  Intializes the LCD **************************
process(RESET,CLK_4M,ns_1,lcd_posedge_s)
begin
     if(RESET = '1') then
         ps_1 <= func_set0;
    elsif(CLK_4M'event and CLK_4M = '1') then
        if(lcd_posedge_s = '1') then
            ps_1 <= ns_1;
        end if;
    end if;
end process;
 
--next state decoder
process(ps_1)
begin
 
      case ps_1 is 
        when func_set0 =>    ns_1 <= func_set0_t;
        when func_set0_t => ns_1 <= func_set0_t1;
        when func_set0_t1 => ns_1 <= func_set0_t2;
        when func_set0_t2 =>    ns_1 <= func_set1;
        when func_set1 =>    ns_1 <= func_set1_t;
        when func_set1_t => ns_1 <= func_set2;
      when func_set2 =>    ns_1 <= func_set2_t;
        when func_set2_t => ns_1 <= func_set3;
        when func_set3 =>    ns_1 <= func_set3_t;
        when func_set3_t => ns_1 <= disp_ctrl;
        when disp_ctrl =>    ns_1 <= disp_ctrl_t;
        when disp_ctrl_t => ns_1 <= cur_set;    
       when cur_set  =>     ns_1 <= cur_set_t;
        when cur_set_t =>   ns_1 <= mode_set;
        when mode_set =>     ns_1 <= mode_set_t;
        when mode_set_t =>  ns_1 <= ddram_add;
      when ddram_add =>    ns_1 <= ddram_add_t;
        when ddram_add_t => ns_1 <= clear_disp; 
        when clear_disp =>   ns_1 <= clear_disp_t;
        when clear_disp_t =>    ns_1 <= wait_state1;
-- LCD intialization FSM locks itself in wait_state1 after intialization is over
        when wait_state1 => ns_1 <= wait_state1; 
        when others =>       ns_1 <= func_set0;
   end case;
end process;
 
--process output decoder
process(ps_1)
begin
 
      case ps_1 is 
            when func_set0 => 
                        refresh <= '0'; 
                        en1 <= '1';
                        data_s <=  "0000110000";
            when func_set0_t => 
                        refresh <= '0'; 
                        en1 <= '0';
                        data_s <=  "0000110000";
                when func_set0_t1 => 
                        refresh <= '0'; 
                        en1 <= '1';
                        data_s <=  "0000110000";
                when func_set0_t2 => 
                        refresh <= '0'; 
                        en1 <= '0';
                        data_s <=  "0000110000";
                when func_set1 =>
                        refresh <= '0'; 
                        en1 <= '1';
                        data_s <=  "0000110000";
            when func_set1_t =>
                       refresh <= '0'; 
                       en1 <= '0';
                       data_s <=  "0000110000";
            when func_set2 =>
                       refresh <= '0'; 
                       en1 <= '1';
                        data_s <=  "0000110000";
            when func_set2_t =>
                       refresh <= '0'; 
                       en1 <= '0';
                        data_s <=  "0000110000";             
            when func_set3 =>
                       refresh <= '0'; 
                       en1 <= '1';
                       data_s <= "0000111000";
            when func_set3_t =>
                       refresh <= '0'; 
                       en1 <= '0';
                       data_s <= "0000111000";
            when disp_ctrl =>
                       refresh <= '0'; 
                       en1 <= '1';
                        data_s <= "0000001110";
            when disp_ctrl_t =>
                      refresh <= '0'; 
                      en1 <= '0';
                       data_s <= "0000001110";
            when cur_set  =>
                      refresh <= '0'; 
                      en1 <= '1';
                      data_s <= "0000011100";
            when cur_set_t  =>
                      refresh <= '0'; 
                      en1 <= '0';
                       data_s <= "0000011100";                  
            when mode_set =>
                      refresh <= '0'; 
                      en1 <= '1';
                      data_s <= "0000000110" ;
            when mode_set_t =>
                    refresh <= '0'; 
                    en1 <= '0';
                    data_s <= "0000000110" ;
                when ddram_add =>
                    refresh <= '0'; 
                    en1 <= '1';
                    data_s <= "0010000000"; 
                when ddram_add_t =>
                    refresh <= '0'; 
                    en1 <= '0';
                    data_s <= "0010000000"; 
            when clear_disp =>
                    refresh <= '0'; 
                    en1 <= '1';
                    data_s <= "0000000001";
            when clear_disp_t =>
                    refresh <= '0'; 
                    en1 <= '0';
                    data_s <= "0000000001";
            when wait_state1 =>     
                      refresh <= '1';
                  en1 <= '0';                           
                   data_s <= "0000000000";
            when others =>
                  refresh <= '0'; 
                    en1 <= '0';
                    data_s <= "0000000000";
     end case;
end process;
--********LCD Intialization ENDS HERE **************************
 
 
--- *******  This FSM writes Data to LCD.
--- This FSM starts after the LCD Initialization is over
process(RESET,CLK_4M,refresh,lcd_posedge_s)
begin
     if(RESET = '1') then
         refresh_d <= '0';
    elsif(CLK_4M'event and CLK_4M = '1') then
        if(lcd_posedge_s = '1') then
            refresh_d <= refresh;
        end if;
    end if;
end process;
 
refresh_s <= '1' when (refresh = '1' and refresh_d = '0') else
             '0';          
 
 
--state2
process(RESET,CLK_4M,lcd_posedge_s)
begin
     if(RESET = '1') then
           prst <= wait_state2;
    elsif(CLK_4M'event and CLK_4M = '1') then
        if(lcd_posedge_s = '1') then
           prst <= nxt;
        end if;
    end if;
end process;
 
 
process(prst,refresh_s)          
begin
     case prst is
-- loop in wait state2 till the LCD is being Intialized
        when wait_state2 =>
        if(refresh_s = '1') then    nxt <= idle1;
                                  else nxt <= wait_state2; --
          end if;
        when idle1 =>  nxt <=idle; 
        when idle =>  nxt <= M;
        when M =>  nxt <= E;
        when E =>  nxt <= C;
        when C =>  nxt <= H;
        when H =>  nxt <= A;
        when A =>  nxt <= T;
        when T =>  nxt <= R;
        when R =>  nxt <= O;
        when O =>  nxt <= N;    
        when N =>  nxt <= I;    
        when I =>  nxt <= C1;   
        when C1 => nxt <= S;        
        when others => nxt <= wait_state2;
     end case;
end process;
 
--output decoder
process(prst)
begin
 
case prst is
 
          when wait_state2 =>
                     data_s1 <= "0000000000";
                 
                        
            when M =>  data_s1 <=  "1001001101";  
            when E =>  data_s1 <=  "1001000101";   
            when C =>  data_s1 <=  "1001000011";  
          when H =>  data_s1 <=  "1001001000";  
           when A =>  data_s1 <=  "1001000001";  
           when T =>  data_s1 <=  "1001010100"; 
           when R =>  data_s1 <=  "1001010010";  
           when O =>  data_s1 <=  "1001001111";  
            when N =>  data_s1 <=  "1001001110";  
            when I =>  data_s1 <=  "1001001001";  
            when C1 =>  data_s1 <=  "1001000011";  
            when S =>  data_s1 <=  "1001010011";  
              
           when others => 
                    data_s1 <= "0000000000";
                        
     end case;     
end process;
                                                                                                        
LCD_D   <= data_s(7 downto 0) or data_s1(7 downto 0);
 
LCD_RS     <= data_s(9) or data_s1(9);
LCD_RW     <= data_s(8) or data_s1(8);
LCD_E     <= en1 or en2;
 
 
end Behavioral;

---

 

[barry]

1) That's pretty presumptuous of you to demand an "urgent solution today" and "all seniors to provide solution". Why should we, because you say we should? Maybe you should try a different approach.

2)Line numbers would help.

 

[ads-ee]

Not out of any interest to help the OP, but only because I couldn't see anything wrong with the file. I tried synthesizing the file and it only had warnings about some signals reducing to a logic 0 after synthesis.