Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Need to write verilog code for following case

Status
Not open for further replies.

kth_hkt

Newbie
Joined
Dec 9, 2020
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
25
I have a memory of depth 4 and 8 bytes wide.
I need to read first two bytes of first address of the memory and calculate its sum and find the average and replace the first two bytes of first address by that average.
Then I need to read the contents of subsequent two bytes of the first address itself and again do sum and find average and then replace third and fourth bytes by that average. This process should continue for all the addresses .
Ex: If the memory is something like this
31243553
22113133
42020464
28268097

Then, first two bits of first address must be replaced by (3+1)/2 = 2
and then next two bits of address must be replaced by (2+4)/2=3,
and so on, for all bytes of all the addresses
Finally the memory should look like,

22334444
22112233
33112255
55444488


I need to write verilog code for this design and the code should be parameterized such that it can be extended to any width and any depth.
 
Last edited:

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
23,018
Helped
4,715
Reputation
9,446
Reaction score
5,087
Trophy points
1,393
Activity points
152,504
Hi,

I´m totally confused.
Nothing matches.

I have a memory of depth 4 and 8 bits wide.
so 4x 8 bits = 4 x 1 byte.
one bit can have the value 0 or 1. so why does you table show values > 1?
did you confuse bits and bytes?

Then, first two bits of first address must be replaced by (3+1)/2 = 4
Formula is wrong

and then next two bits of address must be replaced by (2+4)/=3,
Formula is wrong

What does your table show? What are the columns? what are the rows? --> give description, work with colors.

Klaus
 

kth_hkt

Newbie
Joined
Dec 9, 2020
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
25
Hi,

I´m totally confused.
Nothing matches.


so 4x 8 bits = 4 x 1 byte.
one bit can have the value 0 or 1. so why does you table show values > 1?
did you confuse bits and bytes?


Formula is wrong


Formula is wrong

What does your table show? What are the columns? what are the rows? --> give description, work with colors.

Klaus
Yes, I got confused with bits and bytes and made appropriate edits in the question.
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
23,018
Helped
4,715
Reputation
9,446
Reaction score
5,087
Trophy points
1,393
Activity points
152,504
Hi,

so the math is clear so far (I hope).

Please provide clear descriptions, like
* one table row shows the contents (8 bytes, starting from left side) of one address (0...3)
(often bit order / byte order is descending, thus the other way round than in your example)

so the system should be (like may systems)
INPUT --> CALCULATE --> OUTPUT

you need to clarify:
* How do you access the input and the output?
* What if the sum of two numbers is an odd value?
* What is your system clock freuquency?
* What is the memory timing?
* What is the calculation timing?

Klaus
 

kth_hkt

Newbie
Joined
Dec 9, 2020
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
25
Hi,

so the math is clear so far (I hope).

Please provide clear descriptions, like
* one table row shows the contents (8 bytes, starting from left side) of one address (0...3)
(often bit order / byte order is descending, thus the other way round than in your example)

so the system should be (like may systems)
INPUT --> CALCULATE --> OUTPUT

you need to clarify:
* How do you access the input and the output?
* What if the sum of two numbers is an odd value?
* What is your system clock freuquency?
* What is the memory timing?
* What is the calculation timing?

Klaus
In first clock pulse all the 8 bytes are read from the first address and added in pairs and and then average is calculated and replaced. All these things occur in one clock pulse i.e. [(3+1)/2], [(2+4)/2],[(3+5)/2] and [(5+3)/2] this calculation and replacement. Therefore, after 4 clock pulses in this case the total memory gets updated with the corresponding average values. There are no other constraints I can think of now.
 

ads-ee

Super Moderator
Staff member
Joined
Sep 10, 2013
Messages
7,935
Helped
1,822
Reputation
3,654
Reaction score
1,806
Trophy points
1,393
Location
USA
Activity points
60,129
If you are supposed to read and write in the same clock cycle then it's probably not something you want to do in an SRAM as that requires a dual port SRAM with a read before write behavior that works.

As this is homework you won't get someone to write this for you. You should start by breaking this down into smaller pieces.

  1. what are your input and output ports on the module? ... read about how to write the module ports and how to use parameters
  2. how are you going to define your "memory"?... read about Verilog arrays
  3. how do you write a register?... look for examples of basic logic written in Verilog
  4. how do you index (count) through the memory "addresses"?... read about counters
  5. how to you use the address to select the correct memory address (assuming you are using registers for the memory)? ... read about multiplexers and de-multiplexers.
  6. how are you going to determine your code works?...read about testbenching.
That should get you started on what you need to know to do your homework.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top