need to select topic for PG degree - LVDS, PLL or ADC?

[amit.dounde]

help me pls

i need to select a topic for my PG degree. we have to give the topics by next week. i have shortlisted a few.
1. on LVDS(low voltage differential signalling)
2. PLL
3. time stretch ADC

i am not sure whether these projects can be completed in one year. also not sure of which ieee paper to select in each.
If anyone reading this post is working in any industry related to analog design please let me know whether these topics are good and whether these topics are in work in industries.

thank you

 

[Sadegh.j]

Re: help me pls

I have designed a PLL in one month, it was intense though, as the PLL did not lock for a while. Basically, it all depends on your PLL specs. Then I designed another PLL, with much more tighter restrictions in three months, I had the experience of the first PLL though. My third PLL design took me only a week, or so.

I have not persoally designed the other blocks.

 

[Teddy]

help me pls

All three topics are very basic and common. You can find tons of stuff on it.
PLL is now "anybody could do it" stuff. Unfortunately it is PLL and PLL. It is easy to do simple one which just locks, but to make one which works on silicon and could sell is different question.
I would prefer the ADC.
If you want to do LVDS - then really high freqency.

 

[gaboor]

help me pls

Pll sounds good and you can find tones of stuff on the web

 

[amit.dounde]

Re: help me pls

appreciate your replies. I was also thinking of TS ADC. but i am not able to find any good material and papers.
one more thing, has anyone done TS ADC in cadence .18um. Any information in this would be helpful

 

[amit.dounde]

Re: help me pls

if i choose LVDS for my project what could be the min. data rate that i need to choose.

thanks