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[SOLVED] need some help with JFET signal bypassing (ala old stomp pedals)

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maark6000

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Hello all, need to ask a question of the JFET wizards out there...

I'm trying to wrap my head around JFET bypassing, in other words using a JFET as an analog switch to either let a signal pass unimpeded or clamp it down so that no AC signal flows. In the attached schematic I've cobbled together the basic theme you see in many guitar pedal schematics. I've built this circuit, and I can't get it to work, and I'm stumped as to why. At the NPN's collector, when the switch is open I'm seeing a voltage of .75 V, and when the switch is closed it's up to 7.96 V. However, at the JFET's gate, the open voltage is .11 V, and not much better when closed at .33 V. I'm not getting the JFET to turn off. I've included the actual devices I'm using, like a J111 and a 1N914 etc... as far as I can tell they have similar characteristics of the devices used in all the various schematics I've seen. The J111 has a Vgs (off) of somewhere between -3 and -10 volts. Also, the AC signal here is audio... so maybe 1 Vpp. Thanks in advance for your help.



- - - Updated - - -

another thought occurs... I'm feeding the drain side of the JFET with a signal generator, a 1 Vpp sine wave, about 300 Hz, and I'm monitoring via my scope what's happening at the "out" pin... and i'm not seeing a reduction at all in the voltage of the sine wave. But, is that what I should expect when the JFET is "off?"
 

The J111 has a Vgs (off) of somewhere between -3 and -10 volts.
Yes, how do you expect to turn it off with maximal -4V Vgs? Did you try to bias source and drain to 8V rather than 4V?

I see guitar amplifiers often using PJFETs like J176 to simplify circuit biasing, allowing turn-off with a single positive control voltage.
 

the 8v scenario occurred to me while I was trying to simulate this whole thing, but I never tried it on the breadboard. I think I was too hung up on why my gate voltage wasn't changing, nor why I wasn't seeing ANY change at all in the AC sine wave. I like the J176 idea, I'll investigate that more.
 

Seeing no gate voltage (I guess with a multimeter or oscilloscope) is expectable by design, because there's no pull-up connected to gate node. Only diode and FET leakage currents (might be < nA order of magnitude) will discharge the gate capacitance.

Usually you would provide a high ohmic pull-up resistor from gate to source and/or drain, particularly if you want defined finite switching time.
 

Today I developed a circuit with a p-channel JFET (like a J176) and got it to work in the Falstad simulator! Pretty excited. I'll try to build it tomorrow on the breadboard and see how well it functions. If it works I'll post the schematic here, perhaps you could help me fine tune it (read: idiot check it). thanks again!
 

okay, check it out, I think I've figured this out. First mistake I made was using a J111 Jfet. I measured it having a Vgs(off) of over 8 volts... and with that diode in there it would never turn off. Do you see any issues with this schematic? It models in Falstad, I've biased everything to be able to pass a pretty large AC signal... 3 Vpp, given my 8 volt high supply rail. The JFET would ideally need a Vgs (off) at -3 volts, which when you bias the source and drain at +4.5 V gives you a nice range between the rails of +6 and +3, just squeaking over the Vgs(off) parameter.

 
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I don't think that the circuit is improved. It's still not achieving reliable turn-off over FET Vp range, at least for 2N5458. And the gate current will cause some signal distortion with higher signal voltages.
 

ok, not giving up! check out this one. I put the diode back in... does this help with gate current / distortion? I've also switched the JFET, to a J112, or I could use a J304 as well, has a very similar Vgs(off), not sure which would be better. I've finally breadboarded this out with a J112 and it's looking good. Had to tweak a few of the voltage divider figures. With a 3 Vpp AC signal flowing through when the switch is closed, it's clamping the signal down to a negligible 60mV(pp) with the switch open. Thoughts?

 

If it is for a Geetar then the distortion is welcomed.

I think for me, since I'm just learning all of this stuff, I'm trying to not purposefully run into clipping of the signal... I need to learn how to find the right bias points in all sections of this particular pedal, which is a bucket-brigade style delay. :)
 

As first step, I suggest a slight modification of the original circuit, as previously mentioned.

mod.png
 
okay, i built the above circuit and WOW!, that's looks good. My scope can't even measure the signal when the JFET is off at lower frequencies (300 Hz). I do notice that at higher frequencies (5k) you start to see a small signal.

So I have two questions... as my scope measures it at the Source... the 3 Vpp AC signal is between 6.3v and 3.3v. But isn't it receiving a 8 volt bias voltage? Wouldn't one expect to see the AC signal higher?

My other question is I measure 4 volts at the gate when the switch is closed. But with a low of 3.3v at the source (assuming my measurement is correct) at the low point of the AC signal, would the JFET not be no longer reverse biased? Unfortunately Falstad doesn't help me too much here, the voltages model differently in that application.

Thanks again for your help...
 

oops, hang on, i realized I was reading the wrong thing on my scope. AC signal at the Source is between 9.4v and 6.3v. Nevermind. :)
 

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