Need some advices about implement H.264 on FPGA (small part)

[win3y]

I am going on implementation H.264 on FPGA namely as "calculate SAD by using 2-D tree architecture and implement it on FPGA (on platform FPGA such as HBE)". I think that it include 3 parts as below:
- Input modulle is to get and process pixel on RAM
- Calculate modulle is to calculate SADmin
- Output modulle is to get data.
But now I have to face to a big problem that how to make input modelle code (to get pixel from RAM on FPGA)
Maybe my solution is wrong? please give me some advices.
Every comments are wellcome.
Thank you in advance.