cl254
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Hi All,
Please explains or point me to some good resources on advanced DRAM timing settings from BIOS. Verbal explanations for some of these timing parameters could be found on the web (see the end), I am looking for clearer details, and their relationships with tRAS, tCAS and other standard DRAM timing parameters. I believe timing diagrams would be very helpful.
The DRAM timing parameters I am trying to understand are:
tWRDD, tWRDD, tWWDD, tWWDR, tRRDD, tRRDR, tRWSR, tRWDD, tRWDR. Maybe there are more.
In addition to the above DRAM timing parameters, these DRAM latency timing parameters need explanation as well:
DRAM TRL
DRAM IOL
THANK YOU VERY MUCH!!! :-D
p.s. web notes on timing parameters:
read to read delay across DIMMS (tRRDR / tRRDD); write to write delay across DIMMS (tWWDR / tWWDD); read to write delay across DIMMS (tRWDRDD / tRWSR); and write to read delay across DIMMS (tWRDRDD)
Please explains or point me to some good resources on advanced DRAM timing settings from BIOS. Verbal explanations for some of these timing parameters could be found on the web (see the end), I am looking for clearer details, and their relationships with tRAS, tCAS and other standard DRAM timing parameters. I believe timing diagrams would be very helpful.
The DRAM timing parameters I am trying to understand are:
tWRDD, tWRDD, tWWDD, tWWDR, tRRDD, tRRDR, tRWSR, tRWDD, tRWDR. Maybe there are more.
In addition to the above DRAM timing parameters, these DRAM latency timing parameters need explanation as well:
DRAM TRL
DRAM IOL
THANK YOU VERY MUCH!!! :-D
p.s. web notes on timing parameters:
read to read delay across DIMMS (tRRDR / tRRDD); write to write delay across DIMMS (tWWDR / tWWDD); read to write delay across DIMMS (tRWDRDD / tRWSR); and write to read delay across DIMMS (tWRDRDD)