Need Pipeline Multiplier RTL

[eda_wiz]

rtl multiplier

Does anyone have a pipelined multiplier code..

 

[jimjim2k]

pipeline rtl

Hi

Here is a bit:

1. h**p://www.doulos.com/knowhow/verilog_models/8bit_x_8bit_pipelined_multiplier/


* -> t

tnx

 

[jimjim2k]

pipeline multiplizierer

Bonjour,

Regarder le URL suivant :

1. h**p://tima-cmp.imag.fr/~guyot/Cours/Oparithm/francais/Multip.htm
2. h**p://tima-cmp.imag.fr/~guyot/Cours/Oparithm/francais/Op_Ar2.htm


* ->t

merci


A funny French note done by systran!!:

Hi,

Look at the following URL:


1. h**p://tima-cmp.imag.fr/~guyot/Cours/Oparithm/francais/Multip.htm
2. h**p://tima-cmp.imag.fr/~guyot/Cours/Oparithm/francais/Op_Ar2.htm


* ->t

thanks

 

[eda_wiz]

pipelined multiplier rtl

hi Jim... thnks for those links...

CAn anyone just tell that whether u /anyone u know have worked on 8*8 multiplier which can be clocked at minimum 100 Mhz...

thanks

 

[patrickli]

pipeline multiplier rtl

It is up to what lib you want to use. 0.13, 0.18 should be OK in 100M.
You can use DW to try in DC.

 

[eda_wiz]

multiplier rtl

Hi patrickli,
I compiled DW multiliplier for TSMC .18 u... but delay I am getting is very high....well can u please say what speed u got for .18u and .13u DW multiplier..

 

[the_penetrator]

be careful wizkid!

if you have acquired TSMC 0.18 from the Artisan pack, something strange is going on. I believe they have changed the absolute values for the timing of their cells.

This is the only explanation i have for some measurements of mine.

Try UMC from Artisan, it may have real values. By the way, in some text in the Artisan pack, "Condition of Terms"-style they state it in law terms --but not very clearly of course.

the_penetrator©

 

[eda_wiz]

ok...
penetrator I have a question for u... what will be the delay difference for a same design in .35 and .18 u technology..

say in .35u if a design runs @ 100Mhz..
what speed approx I cud expect in .18 or .13 u process.

 

[gerade]

from my experience, even for 0.25 32 bit multiplier can be synthesis out