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paper help!
hi,
I need some paper related the all digital PLL. please help me to download the paper!
Thank you !
Paper list:
[1] R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, “A first
multigigahertz digitally controlled oscillator for wireless applications,”
IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 11,
pp. 2154–2164, Nov. 2003.
[2] R. B. Staszewski and P. T. Balsara, “All-digital PLL with ultra fast
settling,” IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 54, no. 2, pp. 181–185, Feb. 2007.
[3] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive
bandwidth control,” IEEE Journal of Solid State Circuits, vol. 35, no. 8,
p. 1137, August 2000.
[4] W. Chaivipas and A. Matsuzawa, “Analysis and design of direct reference
feed-forward compensation for fast-settling all-digital phase-locked loop,”
IEICE Transactions on Electronics, vol. E90, no. 4, pp. 793–801, April
2007.
[5] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital
phase-locked loop with 50-cycle lock time suitable for high-performance
microprocessors,” IEEE Journal of Solid-State Circuits, vol. 30, no. 4,
pp. 412–422, April 1995.
[6] R. B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and
P. T. Balsara, “All-digital phase-domain TX frequency synthesizer for
bluetooth radios in 0.13 μm CMOS,” 2004.
[8] S. Mendel and C. Vogel, “A z-domain model and analysis of phasedomain
all-digital phase-locked loops,” in Proceedings of the 25th IEEE
Norchip Conference, 2007, Aalborg, Denmark, 19-20 Novemeber 2007.
hi,
I need some paper related the all digital PLL. please help me to download the paper!
Thank you !
Paper list:
[1] R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, “A first
multigigahertz digitally controlled oscillator for wireless applications,”
IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 11,
pp. 2154–2164, Nov. 2003.
[2] R. B. Staszewski and P. T. Balsara, “All-digital PLL with ultra fast
settling,” IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 54, no. 2, pp. 181–185, Feb. 2007.
[3] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive
bandwidth control,” IEEE Journal of Solid State Circuits, vol. 35, no. 8,
p. 1137, August 2000.
[4] W. Chaivipas and A. Matsuzawa, “Analysis and design of direct reference
feed-forward compensation for fast-settling all-digital phase-locked loop,”
IEICE Transactions on Electronics, vol. E90, no. 4, pp. 793–801, April
2007.
[5] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital
phase-locked loop with 50-cycle lock time suitable for high-performance
microprocessors,” IEEE Journal of Solid-State Circuits, vol. 30, no. 4,
pp. 412–422, April 1995.
[6] R. B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and
P. T. Balsara, “All-digital phase-domain TX frequency synthesizer for
bluetooth radios in 0.13 μm CMOS,” 2004.
[8] S. Mendel and C. Vogel, “A z-domain model and analysis of phasedomain
all-digital phase-locked loops,” in Proceedings of the 25th IEEE
Norchip Conference, 2007, Aalborg, Denmark, 19-20 Novemeber 2007.