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Sreenivas said:Dear Friend,
When you are working on DLL for higher frequency it is the delay stages(VCDL) is really challenging and crucial design and other thing that is of interest is you should take care of that your DLL should not able to lock at 2T,3T,4t.......etc.......except that it should always lock to 1T, which can obtained using start controlled PFD and false lock decoding circuit.