need info about synthesizing modelsim files in xilinx

[aravindh91]

i have written a code in modelsim and i have checked it in its simulation now i want to synthesize it in xilinx when i import the code from the modelsim directory and check for no errors occur but when starting implementation it shows no library is found
i have used a created library named lowaop in the code , i hope that since i created a library lowaop in modelsim it is not working in xilinx and shows synthesis failed .
how can this problem can be solved pls give me necessary steps to synthesize the code
thanks in advance

 

[aruipksni]

i have written a code in modelsim and i have checked it in its simulation now i want to synthesize it in xilinx when i import the code from the modelsim directory and check for no errors occur but when starting implementation it shows no library is found
i have used a created library named lowaop in the code , i hope that since i created a library lowaop in modelsim it is not working in xilinx and shows synthesis failed .
how can this problem can be solved pls give me necessary steps to synthesize the code
thanks in advance

you need to map your libraray to your vhdl source files.
just do "add library" from the ise gui, use same library refference you have made when working with modelsim, and select when your source files are at.
you can also do it manually like modelsim "vmap" by editing xst.prj file.