Need info about designing clock dividers

[badola]

do anyone of u have clock divider circuits design manual.???? can u send me books or link from where i can get this?????

 

[research_vlsi]

Re: clock dividers



this shall be useful for u

 

[badola]

Re: clock dividers

thanks.......................

 

[srik_naidu]

Re: clock dividers

Hi,

T-FF will be a clock divider.
Input to T-FF is logic-1 always
Output of T-FF is always toggled w.r.t input clk.
the frequency will be half the input clk.

Thanks & Regards,
Sri.

 

[NAresh123]

clock dividers

hi i need also

 

[Arturi]

Re: clock dividers

To divide by 2 you can simply use a toggle flop.
In other words you connect the QN output to the D input of the flop. The Q output will toggle with half the frequency of the clock you connect to the CLK port of that flop.

 

[nileshprasad]

Re: clock dividers

thanks!!!... good info

 

[sree205]

clock dividers

 

[shiv_emf]

clock dividers

I think u want to knw about programmable divider?

 

[surisingh]

Re: clock dividers

Hi,
You can find out the general concept to design any divide by odd counter in my blogspot.

https://chipverification.blogspot.com/2008/05/clock-dividers.html

Regards,
CSuresh

 

[Nir Dahan]

clock dividers

this small paper from xilinx is also useful but contains designs with combinational loops.
**broken link removed**

you can also take a look at my blog, there is a question dealing with a divide by 3 circuit with 50% duty cycle (as in the above post)
the problem:
https://asicdigitaldesign.wordpress...w-question-for-logic-design-a-mini-challenge/
a solution
https://asicdigitaldesign.wordpress...cal-interview-question-the-standard-solution/
a more optimal solution:
https://asicdigitaldesign.wordpress.com/2008/01/31/ultimate-technical-interview-question-take-2/

There is another paper circulating on the web for all odd clock dividers which was very interesting but I can't find it right now.

ND.
https://asicdigitaldesign.wordpress.com/