Need help with the verilog code for RAM 2 port

[Virashree Patel]

Hi , I am starter in HDL coding and still learning how to code in verilog. I am struggling a lot with wire and reg concepts , as I am still learning about the filp flops and basic hardware concepts.


I have attached the image what my project is about. it gives a quick explanation about what I am supposed to build.

I have pasted all my code here. I am being able to see the characters on my sevenseg display for Display 1...5 , Display 6 , 7 shows "00" .

Memory.v is the auto generated file
Memory_internal.v is the top level entity in my project
Memory_internal_tb.v is the test bench file for modelsim

Please help me out to figure out where am i going wrong and feeling totally confused! I need someone to look at my code and tell me at this point! For the project I need to provide both the modelsim simulations and the output on the DE2 board.

Thanks in advance !

Controller.v

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`timescale 100 ns / 1 ns 
module Controller (clk , ar , wren, Done_c ,R,W, Q , A , Din );
 
input ar , clk ;
output reg Done_c ;
output reg wren;
input [7:0] Q ;
input R , W;
//wire q ;
 
 
reg [7:0]counter;
 
input [9:0] A ;
wire [9:0] A_m;
assign A_m = A;
 
input [7:0] Din;
wire [7:0]Din_m;
assign Din_m = Din ;
 
 
reg [7:0]Dout;
 
reg [4:0] cs ;
parameter [4:0] Idle = 4'h0 , WritePushed = 4'h1 , WriteWait1 = 4'h2 ,WriteWait2 = 4'h3, WriteDone = 4'h4 , ReadPushed = 4'h5 , 
ReadWait1 = 4'h6 ,ReadWait2 = 4'h7 , ReadDone = 4'h7 , ReadWait3 = 4'h8 , Default = 4'h9;
 
Memory ram ( .clock(clk) , .rdaddress(A_m) , .wraddress(A_m) , .wren(W) , .q(Q) , .data(Din_m));
 
always @ (posedge clk or negedge ar)
    if(~ar)
        cs = Idle;
        
        else 
    begin 
        case(cs)
            Idle:
                begin 
            if(R == 1)
                cs = ReadPushed;
            else if(W == 1)begin 
                wren = W;
                cs = WritePushed;end 
            else begin 
                cs = Idle ;
                Done_c = 0;end 
                
                counter = 0;
            end
//write:
 
            WritePushed:
                begin 
                if(wren == 1)
                begin 
                    Done_c = 0;
                    counter = 0;
                
                    cs = WriteWait1;
                end
                end 
             
            WriteWait1:begin 
                    counter = counter + 1;
                    if(counter == 2)
                            cs  = WriteDone;
                        else  
                            cs = WriteWait1;
                    end  
       
            WriteDone:
                begin
                counter = 0;
                Done_c = 1;
                cs = Idle;
                end 
                
            //read
            ReadPushed:
                begin 
                    if(R == 1)begin 
                    counter = 0;    
                    cs = ReadWait1;end 
                end 
                
            ReadWait1:begin 
                counter = counter + 1;
                    if(counter == 100)
                        cs = ReadDone;
                    else 
                        cs = ReadWait1;
                    end 
     
            ReadDone: 
                begin 
                counter = 0;
                //Q = q;
                //Dout = Q;
                    Done_c = 1'b1;
                    cs = Idle ;
                end
     
            Default:
                begin counter = 0;
                    cs = Idle ;
                end 
    endcase 
        end 
            endmodule

---

Memory_internal.v (top level entity)

---

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`timescale 100 ns / 1 ns 
 
module Memory_internal (clk , ar , A_dip , D_dip , LEDgreen , WritePush , ReadPush , Display1 , Display2 , Display3 , Display4 , 
                        Display5 ,Display6 ,Display7, LEDred , TestPush , R_enable , W_enable );
 
input clk , ar;
wire Done ;
 
input [9:0] A_dip ;
input [7:0] D_dip ;
input ReadPush , WritePush , TestPush;
//wire [9:0] AddressGen;
//wire [7:0] DataGen;
wire [7:0]Dout_wire  ; 
output reg [6:0] Display1 , Display2 , Display3 ,Display4 , Display5 , Display6 ,Display7; 
output reg LEDgreen , LEDred; 
output reg R_enable , W_enable ;
assign R = R_enable ;
assign W = W_enable;
 
reg ReadPush_prev , WritePush_prev , TestPush_prev; 
reg [7:0]counter;
 
reg [9:0] A;
wire [3:0]A1 , A2 ,A3;
assign A1 = {2'b00 , A[9:8]};
assign A2 = A[7:4];
assign A3 = A[3:0];
 
reg [7:0]Din;
wire [3:0] D1 , D2;
assign D1  = Din[7:4];
assign D2 = Din[3:0];
 
reg [7:0]Data;
wire [3:0] Data1 , Data2 ;
assign Data1 = Dout_wire[7:4];
assign Data2 = Dout_wire[3:0];
 
wire [6:0]A1Display , A2Display , A3Display, D1Display , D2Display , Dout1Display ,Dout2Display ;
 
reg [4:0]cs;
parameter [4:0] Idle = 5'h0 , WritePushed = 5'h1 , WriteWait2 = 5'h3 ,WriteWait1 = 5'h4 , WriteDone = 5'h5 , Default = 5'h6,
ReadPushed = 5'h7, ReadWait1 = 5'h8,ReadWait2 = 5'h9 , DoneRead = 5'hA , Idle_read = 5'hB , Push = 5'hC , DoneWrite = 5'hD,
Auto = 5'hE ,Delay = 5'hF ,  TestPushed = 5'h10 , AutoRead = 5'h11 , AutoWrite = 5'h12 , Delay1 = 5'h13 , Delay2 = 5'h14 ;   
 
SevenSeg decoder1(.Input(D1) , .Display(D1Display));
SevenSeg decoder2(.Input(D2) , .Display(D2Display));
SevenSeg decoder3(.Input(A1) , .Display(A1Display));  
SevenSeg decoder4(.Input(A2) , .Display(A2Display));
SevenSeg decoder5(.Input(A3) , .Display(A3Display));
SevenSeg decoder6(.Input(Data1) , .Display(Dout1Display));
SevenSeg decoder7(.Input(Data2) , .Display(Dout2Display));
//LFSR lfsr (.clk(clk) , .ar(ar) ,.AddressGen(AddressGen) , .DataGen(DataGen));
Controller readwrite (.clk(clk) , .ar(ar) , .R(R) , .W(W) , .Done_c(Done) , .Q(Dout_wire) , .A(A) , .Din(Din) );
 
//==============================================================//
 
always@(negedge ar or posedge clk)
begin 
if(~ar)
    ReadPush_prev = 1'b0;
  else 
    ReadPush_prev = ReadPush;
end 
 
always @(negedge ar or posedge clk)
begin 
  if(~ar)
    WritePush_prev = 1'b0;
  else 
    WritePush_prev = WritePush;
  end 
 
  always@(negedge ar or posedge clk)
  begin 
  if(~ar)
        TestPush_prev = 1'b0;
    else 
        TestPush_prev = TestPush ; 
  end 
   
always@(negedge ar or posedge clk)
 
if(~ar)
  begin 
    cs = Idle;
     LEDgreen = 1'b0;
     LEDred = 1'b0;
        Display1 =  7'b1000000;
      Display2 = 7'b1000000;
      Display3 = 7'b1000000;
        Display4 = 7'b1000000;
      Display5 = 7'b1000000;
        Display6 =7'b1000000;
      Display7 = 7'b1000000;
  end 
  
else 
 
begin 
 case(cs)
   
   Idle: begin   
                if(ReadPush == 1'b0 && ReadPush_prev == 1'b1 && TestPush == 1'b1 )begin
                  cs = ReadPushed; 
                  R_enable =1 ;end
                else if (WritePush == 1'b0 && WritePush_prev == 1'b1 && TestPush == 1'b1)begin
                  cs = WritePushed;
                  W_enable  = 1;
                        LEDgreen = 1'b0;
                        LEDred = 1'b0;end
                    else if(TestPush == 1'b0 && TestPush_prev == 1'b1)begin 
                        cs = Auto ; 
                        end 
                else begin
                  cs = Idle;
                R_enable = 0;
                W_enable = 0;
                counter = 0;
                    
                      end
          end 
        
//Read:
    
    ReadPushed: begin 
     if(R_enable == 1)
      A = A_dip;
      Display1 = A1Display;
      Display2 = A2Display;
      Display3 = A3Display;
      counter = 0;
      cs = ReadWait1;
    end 
        
    ReadWait1:begin 
      counter = counter + 1;
      if(counter == 2)
       cs  = DoneRead;
     else  
       cs = ReadWait1;
     end 
    
     DoneRead: begin 
       if(Done == 1)
         begin 
           R_enable = 0;
           Data = Dout_wire;
           counter = 0;
          Display6 = 7'b0011001;//Dout1Display;
          Display7 = 7'b0011001;//Dout2Display;
          cs = Idle ;
       end 
    // else LEDred = 1'b1;
      end 
         
//Write
    WritePushed:begin 
     if(W_enable == 1)
     begin
      LEDgreen = 1'b0;
        LEDred = 1'b0;
      A= A_dip;
      Display1 = A1Display ;
      Display2 = A2Display;
      Display3 = A3Display;
        
      Din = D_dip;
      Display4 = D1Display;
      Display5 = D2Display;
      counter = 0;
      cs = DoneWrite;
        end 
    end 
    
      DoneWrite: begin 
        if(Done == 1)
          begin
          W_enable = 0;
          LEDgreen = 1'b1;
             LEDred = 1'b0;
          cs = Idle;
        end 
          else if (Done == 0)begin 
          LEDgreen = 1'b0;
          LEDred = 1'b1;
          cs = WriteWait1;end 
          else 
          cs = WriteWait1;
          
      end 
        
        WriteWait1:begin 
       counter = counter + 1;
       LEDgreen = 1'b0;
         LEDred = 1'b1;
      if(counter == 2)
       cs  = DoneWrite;
     else 
       cs = WriteWait1;
       end 
 
            
      Default:
       cs = Idle ;
        
      endcase
    end 
 endmodule    
//======================================================//
  
 module SevenSeg(Input,Display);
    input [3:0] Input;
    output [6:0] Display;
    reg [6:0] Display;
 
    always@(Input)
    //gfedcba
    case (Input)
      
    4'h0 : Display = 7'b1000000;
    4'h1 : Display = 7'b1111001;
    4'h2 : Display = 7'b0100100;
    4'h3 : Display = 7'b0110000;
    4'h4 : Display = 7'b0011001;
    4'h5 : Display = 7'b0010010;
    4'h6 : Display = 7'b0000010;
    4'h7 : Display = 7'b1111000;
    4'h8 : Display = 7'b0000000;
    4'h9 : Display = 7'b0010000;
    4'hA : Display = 7'b0001000;
    4'hb : Display = 7'b0000011;
    4'hC : Display = 7'b1000110;
    4'hd : Display = 7'b0100001;
    4'hE : Display = 7'b0000110;
    4'hF : Display = 7'b0001110;
    default : Display = 7'bx ; 
    
  endcase 
endmodule 
 
//============================================//

---

Memory_internal_tb.v(testbench)

---

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`timescale 1 ns / 1 ns 
 
module Memory_internal_tb;
  
  reg clock ; 
  reg reset ;
  reg  [9:0]A ;
  reg  [7:0]D ;
  wire  Read_enable , Write_enable ; 
  reg ReadPush , WritePush , ReadPush_prev , WritePush_prev , TestPush , TestPush_prev;
  
  wire [7:0]Dout; 
  wire LEDgreen;
  wire LEDred;
    wire Done;
    //parameter bit_period = 104166;
    
wire [6:0]Display1 , Display2 , Display3 , Display4 , Display5 , Display6 , Display7;
 
Memory_internal memory (.clk(clock) , .ar(reset) , .A_dip(A) , .D_dip(D) , .LEDgreen(LEDgreen) , .WritePush(WritePush),
                        .ReadPush(ReadPush) , .Display1(Display1) , .Display2(Display2) , .Display3(Display3) , 
                        .Display4(Display4) , .Display5(Display5) ,.Display6(Display6) ,.Display7(Display7),
                        .Dout(Dout), .R_enable(Read_enable) , .W_enable(Write_enable),.LEDred(LEDred));
 
initial
  begin
     // set to 0 so toggling can occur
     clock = 1'b0;
     reset = 1'b1;   // Start reset at 1
   
    #1 reset = 1'b0; // Set reset to 0 after 5 ns
    #20 reset = 1'b1; // Set reset to 1
   
   // Generates the input values
 
   #10 
   ReadPush = 1'b0 ; 
   ReadPush_prev = 1'b1;
   //Read_enable = 1'b1;
   #2
   A = 10'h123;
  @(posedge clock)
    #2 ReadPush = 1'b1;
    
  @(posedge clock)
   #20
   WritePush = 1'b0 ; 
   WritePush_prev = 1'b1;
   //Write_enable = 1'b1;
   #2
   A = 10'h101;
   D = 8'h20; 
   @(posedge clock)
   #2 WritePush = 1'b1;
 
    @(posedge clock)
    #10 
    TestPush = 1'b0;
    TestPush_prev = 1'b1;
    
  end 
   // Controls the test clock
always
    #12 clock = ~clock;     // For 12 ns period
   
endmodule

---

Memory.v

---

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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram 
 
// ============================================================
// File Name: Memory.v
// Megafunction Name(s):
//          altsyncram
//
// Simulation Library Files(s):
//          altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
 
//Copyright (C) 1991-2013 Altera Corporation
 
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Memory (
    clock,
    data,
    rdaddress,
    wraddress,
    wren,
    q);
 
    input     clock;
    input   [15:0]  data;
    input   [9:0]  rdaddress;
    input   [9:0]  wraddress;
    input     wren;
    output  [15:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
    tri1      clock;
    tri0      wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
 
    wire [15:0] sub_wire0;
    wire [15:0] q = sub_wire0[15:0];
 
    altsyncram  altsyncram_component (
                .address_a (wraddress),
                .clock0 (clock),
                .data_a (data),
                .wren_a (wren),
                .address_b (rdaddress),
                .q_b (sub_wire0),
                .aclr0 (1'b0),
                .aclr1 (1'b0),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),
                .byteena_a (1'b1),
                .byteena_b (1'b1),
                .clock1 (1'b1),
                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .data_b ({16{1'b1}}),
                .eccstatus (),
                .q_a (),
                .rden_a (1'b1),
                .rden_b (1'b1),
                .wren_b (1'b0));
    defparam
        altsyncram_component.address_reg_b = "CLOCK0",
        altsyncram_component.clock_enable_input_a = "BYPASS",
        altsyncram_component.clock_enable_input_b = "BYPASS",
        altsyncram_component.clock_enable_output_a = "BYPASS",
        altsyncram_component.clock_enable_output_b = "BYPASS",
        altsyncram_component.intended_device_family = "Cyclone II",
        altsyncram_component.lpm_type = "altsyncram",
        altsyncram_component.numwords_a = 128,
        altsyncram_component.numwords_b = 128,
        altsyncram_component.operation_mode = "DUAL_PORT",
        altsyncram_component.outdata_aclr_b = "NONE",
        altsyncram_component.outdata_reg_b = "CLOCK0",
        altsyncram_component.power_up_uninitialized = "FALSE",
        altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
        altsyncram_component.widthad_a = 7,
        altsyncram_component.widthad_b = 7,
        altsyncram_component.width_a = 16,
        altsyncram_component.width_b = 16,
        altsyncram_component.width_byteena_a = 1;
 
 
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL "rdaddress[6..0]"
// Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL "wraddress[6..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
// Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Memory_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

---

 

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You need to learn the difference between blocking (=) and non-blocking (<=) assignments. You should search either this forum or use google.
in summary = for combinational logic, <= for sequential logic (i.e. flip-flops).

Also you should use a synchronously deasserted reset, there is an app note on Altera's web site about this.