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Need help with my Delay Locked Loop (DLL) design.

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spec07

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Hi,

I need help with my DLL design which consist of a phase detector, charge pump loop filter and a voltage control delay line(VCDL). The input of the phase detector is fed by 2 clocks (clock reference and output clock with is a feedback from the output of the VCDL. The problem I am facing now is that I am unable to lock the reference clk and output clk despite running the simulation for 300us. I am simulating at 1Mhz for the clock pulses.

Any help and advice would be appreciated.

Thank you.
 

tony_lth

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Maybe you should upload your design, let's check what's wrong.
 

leo_o2

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Please have stability analysis before. Does it have enough phase margin?
 

spec07

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What kind of phase margin are you referring to? Will take screen shot of the schematics and upload asap. Thanks for the prompt replies.
 

spec07

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What is the number of delay stages for the VCDL required for the design if i were to use a current starved inverter? Which means how many current starved inverter I should have? For the 2 input clocks, clk_in which is input to the VCDL and clk_ref which is input to the phase detector, should I set a delay between them?
 
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