[SOLVED] Need help with moving (slow clocked) data using FIFO and DMA to PS of Zynq

[mzeeshanarshad]

Hi,

I'm trying to connect the AD7961 (5MHz) I designed tADC to Zedboard. I got the AD7961 no-os driver module from the AD7961 example project at AD-WIKI site which has the following interface:

module AD7961
    (
        input           m_clk_i,                    // 100 MHz Clock, used for tiing
        input           fast_clk_i,                 // Maximum 300 MHz Clock, used for serial transfer
        input           reset_n_i,                  // Reset signal, active low
        input   [ 3:0]  en_i,                       // Enable pins input
        input           d_pos_i,                    // Data In, Positive Pair
        input           d_neg_i,                    // Data In, Negative Pair
        input           dco_pos_i,                  // Echoed Clock In, Positive Pair
        input           dco_neg_i,                  // Echoed Clock In, Negative Pair
        output  [ 3:0]  en_o,                       // Enable pins output
        output          cnv_pos_o,                  // Convert Out, Positive Pair
        output          cnv_neg_o,                  // Convert Out, Negative Pair
        output          clk_pos_o,                  // Clock Out, Positive Pair
        output          clk_neg_o,                  // Clock Out, Negative Pair
        output          data_rd_rdy_o,              // Signals that new data is available
        output  [15:0]  data_o                      // Read Data
    );

I designed custom IP using AXI4Stream interface and in the default code I replaced the commented line with the assignment to adc_data_reg which gets the value of adc_data_out wire from the ad7961 module.

// Streaming output data is read from FIFO     
     always @( posedge M_AXIS_ACLK )                
     begin                                          
       if(!M_AXIS_ARESETN)                          
         begin                                      
           stream_data_out <= 1;                    
         end                                        
       else if (tx_en)// && M_AXIS_TSTRB[byte_index]
         begin                                      
          // stream_data_out <= read_pointer + 32'b1;
          stream_data_out <= adc_data_reg;
         end                                        
     end

And here's my block design:


I used the data_rd_rdy_out as a clock for the m00_axis and the fifo input. In the SDK I used the DMA to collect data in the DDR but when I check that data its not correct. Whats wrong with this design?
Could you please help me out?

Thanks.

Regards,

Shan

 

[Miralipoor]

Hi,
Unfortunately i could not find your chip (ad79761) . Anyway for troubleshooting try to figure out minimized system. for example you can use simple I/O rather that using DMA. Also check your differential I/O pins and pin numbers.Many thing may occurs you must narrow down your question.What did you expect to read and what did you read. Which parts of your system are suspicious.Ask in details to get answer in details.
Regards

 

[ads-ee]

I'm trying to connect the AD7961 (5MHz) I designed tADC to Zedboard. I got the AD7961 no-os driver module from the AD7961 example project at AD-WIKI site which has the following interface:

This is the problem with so many posters on edaboard. Where is the link to this AD-WIKI site? I did a quick google search and NOTHING comes up. If you want help then give all the information you have...web links, code, testbench, everything you can think of.

Instead you show us...

module AD7961
    (
    );

A useless out of context module port declarations. The module ports don't tell anyone what the module actually DOES!

I designed custom IP using AXI4Stream interface and in the default code I replaced the commented line with the assignment to adc_data_reg which gets the value of adc_data_out wire from the ad7961 module.

...some default code changes, what default code? Oh this must be from the web site that doesn't come up when you search for "AD-WIKI" on google.

And here's my block design:
View attachment 114141

Now you give us a BD picture that doesn't tell us much besides you used the AD7961 module above. Another useless piece of information that won't get you much help.

I used the data_rd_rdy_out as a clock for the m00_axis and the fifo input. In the SDK I used the DMA to collect data in the DDR but when I check that data its not correct. Whats wrong with this design?

Honestly with the lack of information you've given for what you designed, I don't think anyone can tell you what is wrong with your design.

To figure out what is wrong you start debugging the design in a simulator. Start with data you know like the AD7961 output follow it through the design till it gets to someplace that breaks. You just have to take a systematic and logical approach to find the code that doesn't work. I also suspect that using data_rd_rdy out is probably not going to work as a clock. The timing of that signal probably doesn't line up correctly with where you want to sample the data from the module.

Could you please help me out?

I've done what I can to help...firstly suggestions on providing adequate information to allow others to help (links, code, and useful info)...secondly starting from a known good point and following the progression of data through the design until it breaks.

Unfortunately i could not find your chip (ad79761).

Maybe typing it into google correctly would help! AD7961

Anyway for troubleshooting try to figure out minimized system. for example you can use simple I/O rather that using DMA. Also check your differential I/O pins and pin numbers.Many thing may occurs you must narrow down your question.What did you expect to read and what did you read. Which parts of your system are suspicious.Ask in details to get answer in details.

Just replacing stuff (makes more work) and poking around in various spots looking for suspicious stuff never works out well for those attempting to debug in this fashion. Just systematically go through from input to output and find what works and what doesn't. You can either start from the memory and go back to the source or my preference in this case is start with the ADC and you'll probably find it's your interface with the ADC that isn't transferring data properly, or maybe the model for the AD7961 isn't generating data due to some missing sample data file or an incorrect setting.

 

[mzeeshanarshad]

Thanks for your detailed reply. You are right I should have been more specific and more details, references and explanation was required. But its too much I think, I will try to debug my problem and come here when I have a specific problem. Anyway sorry for that. I really appreciate your quick and detailed reply.

Regards,

Shan