Need help with module simulation using ModelSim

[hoangthanhtung]

Simulation with Verilog

I have a module based on Verilog. I also have input/output data files in term text file. Theyt contain signed integers and is generated by Matlab.

I want to Simulation my module by using ModelSim like as

- Read input file correspond with clock signal as a testbench signal
- Simulation by using my module
- Write output of my module to other file (in term of text file)

Is there anybody who can help me ! If you have any example that mention in my problem, could you send to my by email

httung@asic.korea.ac.kr

Thank in advance

 

[jcchan]

Re: Simulation with Verilog

The output text file you can use printf ("%h %h ",var1, var2);

 

[vivek]

Re: Simulation with Verilog

u seem to need file i/o in verilog. This can be done by file i/o commands like fprintf and fscanf in verilog. Refer verilog HDL by Samir palnitkar, u will get a good idea how to do it.