2 .1. Block Diagram Description
The Module contains all the required hardware for device operation such as a line protection network,
ceramic filters, and a power supply. The board performs an asynchronous UART protocol over DC
power lines at data rates of up to 57.6Kbps. Operation at 115.2Kbps requires dedicated filters. The
SIG60 may also be used as a new physical layer to the LIN protocol. The Module can be connected
directly to a host (Micro controller with UART port or a PC) through its JP1 I/O connector. The EVB
block diagram is described in Figure 2.1
The received data signal from the DC line passes through a protection network into the RxIn input pin
to an Rx amplifier. The amplified signal passes via F0B or F1B pins to an external ceramic filter and
back into RxP input. The SIG60 decodes the data and output it to HDO pin as an asynchronous bit
stream.
On the transmitter side, the host sends UART data to the SIG60 via HDI pin. The asynchronous data is
protected against errors and modulated inside the SIG60. The DTXO pin outputs the digitally
modulated signal to the ceramic filter for shaping. The shaped signal enters the SIG60 via F0B or F1B
pins into an output amplifier. The modulated data on TxO pin drives the DC line via the protection
network. To connect HDI and HDO signals to a PC, additional RS232 or USB interface is required.