need HELP with JK Flip Flop in Spectre Cadence

Hi folks,

I'm using a JK flip flop to build a counter in high level, and my flip flop has Clock ,J,K input and Q,Qbar output,
I'm supposed to connect the J and K to high , apply a clock pulse to input ,so it will toggle at clock pulse edges,

But the flip flop doesn't work .and the output is zero ,
I guess its because of the Vdd of circuit and voltage of my clock pulse ,it has something with transition , I put the code of my JK flip flop here, would u please someone look at it and tel me how I should set the clock voltage and my vdd?


module jk_clk_ff(vin_j, vin_k, vclk, vout_q, vout_qbar);
input vin_j, vin_k, vclk;
output vout_q, vout_qbar;
electrical vmodule jk_clk_ff(vin_j, vin_k, vclk, vout_q, vout_qbar);
input vin_j, vin_k, vclk;
output vout_q, vout_qbar;
electrical vin_j, vin_k, vclk, vout_q, vout_qbar;

parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 2.5;
parameter real vtrans = 2.5;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

integer q;

analog begin
@ (cross( V(vclk) - vtrans_clk, +1 )) begin
if (V(vin_j) > vtrans && V(vin_k) > vtrans) begin
q = !q;
end else if (V(vin_j) > vtrans && V(vin_k) < vtrans) begin
q = 1;
end else if (V(vin_j) < vtrans && V(vin_k) > vtrans) begin
q = 0;
end
end

V(vout_q) <+ transition( vlogic_high*q + vlogic_low*!q,
tdel, trise, tfall);
V(vout_qbar) <+ transition( vlogic_high*!q + vlogic_low*q,
tdel, trise, tfall);
end
endmodule