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need help with frequency divider

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barzel

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hi all

i wrote a vhdl code for uart receiver, but i cant get the 9600 bps with my Altera kit.
i use Altera cycloneII FPGA development kit [EP2C20F484C7N].
there is 3 kind of clocks 24Mhz, 27MHz and 50MHz.
my uart code use counter that count a clocks and every 16 ticks its one bit.
thats mean i need 16*9600 = 153600[Hz] frequency. how can i do that?

clock/X=153600 => X=175.78125 [for 27MHz] i divide for 176

i wrote a simple code:

what is wrong or how can i do it better?




Code:
library ieee;
use ieee.std_logic_1164.all;
entity uart_frq is
 generic (	Thigh	: integer := 176);
 
 port(		frqin	: in std_logic;
			frqout	: out std_logic;
			reset	:in std_logic);
end uart_frq;
 
architecture behave of uart_frq is
signal cnt: integer range 0 to Thigh;
	begin
		
		  process(frqin)
		  begin
			if reset='1' then cnt<=0; frqout<='0';
			elsif frqin'event and frqin='1' then 
			cnt<=cnt+1;
			 if cnt<88 then
			 frqout<='1';
			 elsif cnt>=88 then
			 frqout<='0';
			 elsif cnt=176 then cnt<=0;
			 end if;
			end if;
	end process;
end behave;


please help me.
 

FvM

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Except for an actual divider ratio of 177 the code should work. The usual suggestion is to use a clock enable of divided
frequency rather than so-called "ripple clocks". A 153kHz clock enable would be set to '1' only for one sysclk period and used
together with the sysclk.

For a simple example design, the difference between ripple clock and synchronous clock enable doesn't matter so much, but the
synchronous way greatly eases interfacing the UART component with other parts of the design without creating timing problems.

However, as the divider is basically working, the problem (if any) is most likely with your UART design, which is of course
the more challenging part.
 

barzel

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i used 2 uart different codes...

Code:
------------------------------------------------------------------------------- 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 
entity my_rX is 
port ( rst,clk : in bit;
	   data_out : out bit_vector ( 7 downto 0);
	   rx_ser_in : in bit;
	   rx_ready : out bit);

end ; 
architecture behave of my_rX is 
signal cnt  :integer  range 0 to 160; 
signal buf : bit_vector ( 7 downto 0);
signal start,clr,startb,stopb : bit;
begin
process (rx_ser_in,rst,clr)
begin
if rst='1' or clr='1' then start<='0';
	elsif rx_ser_in'event and rx_ser_in='0' then 
			start<='1';
   end if;
end process;

process(CLK,clr,rst) 
begin 
if rst = '1' or clr='1' then 
cnt<=0;
buf<="00000000";
rx_ready <='0';
elsif clk'event and clk='1' then
	if start='1'  then
		if cnt<160 then cnt<=cnt+1; else cnt<=0; end if;
			if        cnt=8        then    startb<=rx_ser_in;
			elsif     cnt=24       then buf(0)<=rx_ser_in;     
		 	elsif     cnt=40       then buf(1)<=rx_ser_in;     
		 	elsif     cnt=56       then buf(2)<=rx_ser_in;     
		 	elsif     cnt=72       then buf(3)<=rx_ser_in;     
		 	elsif     cnt=86       then buf(4)<=rx_ser_in;     
		 	elsif     cnt=102      then buf(5)<=rx_ser_in;     
			elsif     cnt=118      then buf(6)<=rx_ser_in;     
			elsif     cnt=134      then buf(7)<=rx_ser_in;     
			elsif     cnt=150      then stopb<=rx_ser_in;
		 	elsif     cnt=155 and startb='0' and stopb='1' then data_out<=buf; rx_ready<='1';
            end if;
	end if;
end if;
end process;
clr<='1' when cnt=160 else '0';
end behave;

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity uart_receiver is
	generic (sample_rate 			: integer :=15);
	port(clock,Rxd					: in std_logic;
		 Data_Out					: out std_logic_vector(7 downto 0);
		 do_echo					: out std_logic;
		 reset						: in std_logic);
end uart_receiver;

architecture behavioural of uart_receiver is
type state_type is (idle,start,data,stop);
signal state  : state_type;
signal Rxd_Prev,start_detected		: std_logic;
signal Rxd_data						: std_logic_vector(7 downto 0);
begin


	data_process : process(clock,Rxd)
	variable data_sample : natural range 0 to 15 ;
	variable data_index : natural range 0 to 7;
			   begin
			   if reset='1' then do_echo<='0'; state<=idle;
			   elsif clock'event and clock='0' then
				   case state is
					   when idle => data_index := 0; start_detected <= '0'; data_sample := 0;
							if Rxd='0' and Rxd_Prev='1' then
							state <= start;
							do_echo<='0';
							else state <= idle;
							end if;
					   when start => start_detected <= '1';
							if data_sample=7 then
							if Rxd='0' then
							state <= data;
							else
							state <= idle;
							end if;
							end if;
					   when data => 
							if data_sample=7 then
							if data_index<7 then  
								Rxd_Data(data_index) <= Rxd;
								data_index := data_index+1;
								state<=data; 
							else
								Rxd_data(data_index) <= Rxd; 
								state<=stop;
							end if;
							else 
							state <= data;
							end if;
					   when stop =>
					        if data_sample=7 then
					        if Rxd='1' then
					   	    Data_Out <= Rxd_data;
					   	    do_echo<='1';
							end if;
							state <= idle;
							end if; 
						   end case;
					 Rxd_Prev <= Rxd;
					 if start_detected='1' then
					 data_sample := data_sample+1;
					 end if;
				   end if;
end process data_process;	
end behavioural;
 

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