Need help with fifo verification

[netreg]

fifo verification

I am new to verification. For verification of fifo, the components required that I have identified are testbench, DUT, bus function model and scoreboard. Is there a difference between testbench and testcase? And can somebody elaborate on the Bus function model for sync fifo. Am I proceeding in the correct direction.

 

[jbeniston]

verification of fifo

A testbench can include many testcases.

A functional model is a model of the hardware at a higher level of abstraction (E.g. written in SystemC, SpecMan e, etc). Often it is treated as a golden reference model, to which the operation of the DUT is compared.

 

[skyfaye]

fifo testbench example

For any verification, the minimum requirement are BFM to drive stimulus (e.g. Fifo write) and monitor (e.g. Fifo read) to capture the output. Next, optionally, you can choose several approach to check the integrity of the output. Probably the most widely use approach is the score boarding method along with a reference model to predict the expected output. However, this approach is typically not cycle-accurate, only transaction-accurate, but depending on your testplan, this may good enough.

There are no precise definition of testbench. Some people, like myself, consider everything else beside the DUT to be the testbench (e.g. reference model and BFMs) and the testcase to be the entity that uses the testbench to execute the test. This is similar to what you see in the lab. For example, you have the board (DUT) and you use the testbench which include traffic generator (Ixia or SmartBit), signal generator (oscilloscope), and monitors (oscilloscope or LED/LCD display) to test the board.

For your particular problem, you would need a BFM driver to write into the FIFO and a BFM monitor to read the data out. For the BFM driver, you would assert WREN and DATA at the same cycle, but only if the FIFO full is not asserted. For the BFM monitor, you would assert RDEN only if the FIFO empty is false, and depending on your FIFO timing, capture the data the same cycle or the next.

For the reference model, it is straight forward for the normal situation. What goes in comes out, without any changes. So it's simple to predict the expected result. Every time you write to the FIFO, store the same write data in a queue, for example, inside your reference model. Every time you read from the FIFO, compare the read data with the expected data in that queue. They should match.

- Hung

 

[netreg]

verification of a fifo

hey thank you..

 

[aji_vlsi]

testbench for fifo verilog

I am new to verification. For verification of fifo, the components required that I have identified are testbench, DUT, bus function model and scoreboard. Is there a difference between testbench and testcase? And can somebody elaborate on the Bus function model for sync fifo. Am I proceeding in the correct direction.

Getting close to the right direction, so keep going and show us if you face issues. For reference, we have taken similar FIFO design and build SystemVerilog-VMM TB step-by-step and have captured the flow in our book (https://www.systemverilog.us/vmm_info.html). Also we presented this as a Paper in SNUG 06, San Jose. If you are based in Bangalore, India - we offer a incubation facility for upcoming/budding Verif engineers like yourself.

Ajeetha, CVC
www.cvcblr.com

 

[netreg]

verification + fifo + bfm + monitor

Thank you Ajeetha

Added after 11 minutes:

@skyfaye

Regarding the area of scoreboard, monitor and checker. What exactly is the difference between them. Scoreboard : stores the input value (write value) .
Monitor: captures or stores the output value(read value) and Checker compares them. Is this the difference?

 

[ljxpjpjljx]

verification example fifo

I think for fifo verification , you should consider the sync and async fifo ,the depth, the limit condition!

 

[skyfaye]

stores verification fifo method

Scoreboarding is a method of checking the output of the DUT. It encompass the computation of the expected output and using it to check against the actual output. You need know the data from the driver in order to compute the expected output. And you need to get the data from the monitor in order to check against the expected output. Hope that's clear.

- Hung

 

[netreg]

verification of async fifo

hey yes thank you ppl for the help

 

[natg9]

how to do verification of basic fifo

Has anybody come across a specman code for FIFO


kindly share it with me

i need to use it as a reference model in my verification process


thanks
natg