Need help with errors in NC Sim

[cafukarfoo]

Hello,

Here is my situation. Please give me some advice. Thanks.
I have a design written in VHDL and testbench written in Verilog HDL.

When i try to run the simulation using ncsim, i got the message below:
ncvhdl: 05.50-p004: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncvhdl_p: *F,NOLSTD: logical library name STD must be mapped to a design library [11.2].
ncvlog: 05.50-p004: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
file: testbench_db/counter_fv.v
ncelab: 05.50-p004: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
Elaborating the design hierarchy:
Caching library 'worklib' ....... Done
Caching library 'library' ....... Done
ncelab: *E,CUVMUR: instance 'counter_TB.counter1' of design unit 'counter' is unresolved in 'worklib.counter_TB:module'.
karfoo@edaws61 /edavol/vol3/projects/karfoo_test/BIST/vhdl/verif 864> ncsim: 05.50-p004: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncsim: *F,NOSNAP: snapshot 'worklib.counter_TB' does not exist in the libraries.

Below is my ncsim run script:
ncvhdl -cdslib cds.lib -work worklib -linedebug -message /edavol/vol3/projects/karfoo_test/BIST/vhdl/counter.vhdl
ncvlog -update -cdslib cds.lib -work worklib -linedebug -message testbench_db/counter_fv.v
ncelab -update -cdslib cds.lib -work worklib -timescale 1ns/1ps -message worklib.counter_TB
ncsim -update -cdslib cds.lib worklib.counter_TB -gui&

Below is my design in VHDL:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
library STD;
use STD.all;

entity counter is
port (
clk : in std_logic;
rst : in std_logic;
counter_out : out std_logic_vector(3 downto 0));
end counter;

architecture behave of counter is
begin -- behave
process (clk,rst)
begin -- process

if rst = '1' then
counter_out <= "0000";
elsif clk'event and clk = '1' then
counter_out <= "0001";
end if;

end process;

end behave;


Below is my testbench in Verilog HDL:
module counter_TB();

reg clk;
wire [3:0] check;
reg rst;

counter counter1 (.clk(clk), .counter_out(check), .rst(rst));


always begin
#25 clk = 1'b0;
#25 clk = 1'b1;
end

initial begin
#10000 $finish;
end

endmodule