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need help with combinational loops

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K

kcinimod

Member level 3
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Dec 19, 2011
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Code: 
library ieee;
use ieee.std_logic_1164.all;
    
entity counter is
    port( 
        clk_in : in std_logic;
        data : in std_logic;
        enable : in std_logic;
        dout : out std_logic;
		trigger : out std_logic
    );
end counter;

architecture count of counter is

signal data_sync : std_logic_vector(1 downto 0);
signal pre_count : integer;
signal pre_count_1 : integer;
signal pre_count_2 : integer;
signal data_count : integer;


begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            data_sync <= data_sync(0) & data;
        end if;
    end process;

    count_proc : process(enable, clk_in, data_sync(1))
    begin
        if enable = '0' then
            data_count <= 0;
            pre_count <= 0;
            pre_count_1 <= 0;
            pre_count_2 <= 0;
		elsif rising_edge(clk_in) then
			if enable = '1' then
				pre_count <= pre_count + 1;
			end if;
		end if;
        
		if rising_edge(data_sync(1)) then
			if (data_count = 0) then
                pre_count <= 0;
                data_count <= data_count + 1;
            elsif (data_count = 1) then
				if (pre_count > 5) then
					pre_count_1 <= pre_count;
					data_count <= data_count + 1;
				end if;
            elsif (data_count = 2) then
				if (pre_count > 5) then
					pre_count_2 <= pre_count;
					data_count <= data_count - 1;
				end if;
            end if;
            pre_count <= 0;
		end if;
    end process;
    
    compare_proc : process(clk_in)
    begin
        if rising_edge(clk_in) then
            if (data_count = 1 and enable = '1') then
                if (pre_count_1 > pre_count_2) then
                    dout <= '1';
					trigger <= '0';
                elsif (pre_count_1 < pre_count_2) then
                    dout <= '0';
					trigger <= '0';
                end if;
			else
				trigger <= '1';
            end if;            
        end if;
    end process;
end count;
Code: 
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at data_count_1[31]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[31]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[30]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[29]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[28]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[27]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[26]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[25]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[24]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[23]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[22]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[21]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[20]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[19]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[18]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[17]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[16]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[15]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[14]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[13]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[12]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[11]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[10]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[9]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[8]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[7]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[6]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[5]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[4]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[3]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[2]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[1]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":47:2:47:3|Found combinational loop at data_count_1[0]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[31]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[30]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[29]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[28]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[27]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[26]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[25]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[24]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[23]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[22]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[21]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[20]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[19]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[18]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[17]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[16]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[15]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[14]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[13]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[12]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[11]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[10]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[9]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[8]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[7]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[6]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[5]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[4]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[3]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[2]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[1]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_1[0]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[31]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[30]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[29]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[28]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[27]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[26]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[25]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[24]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[23]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[22]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[21]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[20]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[19]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[18]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[17]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[16]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[15]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[14]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[13]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[12]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[11]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[10]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[9]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[8]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[7]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[6]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[5]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[4]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[3]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[2]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[1]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop at pre_count_2[0]
@W: CL169 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":27:8:27:9|Pruning register data_sync(1 downto 0)  
@W: CL159 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\qrng.vhd":7:8:7:11|Input data is unused
@W: BN132 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Removing user instance count_proc.pre_count_2_1[31:0],  because it is equivalent to instance count_proc.pre_count_1_1[31:0]
@W: BN132 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":74:23:74:47|Removing user instance compare_proc.un26_data_count,  because it is equivalent to instance compare_proc.un25_data_count
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[32]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net un2_data_count_1[1]
@W: MO161 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":69:8:69:9|Register bit dout is always 1, optimizing ...
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":34:8:34:9|Found combinational loop during mapping at net count_proc\.pre_count_2_1[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_8
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_9
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_10
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_11
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_12
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_13
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_14
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_15
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_16
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_17
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_18
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_19
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_20
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_21
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_22
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_23
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_24
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_25
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_26
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_27
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_28
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_29
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_30
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_31
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_32
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_33
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_34
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_35
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_36
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_37
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_38
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":50:32:50:47|Found combinational loop during mapping at net N_39
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.un7_data_count_6_0_RNIKAITK
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.data_count_1_6[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.un7_data_count_6_0_RNIA5PEA
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.un7_data_count_6_0_RNILIC75
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.un7_data_count_6_0_RNI8L4R91
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.un7_data_count_6_0_RNIGA9MJ2
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":48:3:48:4|Found combinational loop during mapping at net count_proc\.un7_data_count_6_0_RNI0SKK
@W: MT420 |Found inferred clock counter|clk_in with period 5.00ns. Please declare a user-defined clock on object "p:clk_in"
hi, how can i solve the combinational loops warnings ?
 

it looks verilog or vhdl
after completion do you feel some error in your algorithm ?
 

im sorry, the codes are written in vhdl, simulation of the codes looked fine, its when i tried synthesizing the design using synplify i get these warnings.
 

First remove the enable = '1' comparison inside rising edge, it is not required, since when enable event is triggered, then only the elsif statement will come into execution.

Code: 
    count_proc : process(enable, clk_in, data_sync(1))
    begin
        if enable = '0' then
            data_count <= 0;
            pre_count <= 0;
            pre_count_1 <= 0;
            pre_count_2 <= 0;
		elsif rising_edge(clk_in) then
			if enable = '1' then
				pre_count <= pre_count + 1;
			end if;
		end if;

Also the way of coding is quite messy. Also, you are driving pre_count at two clocks (Clk_in and data_Sync(0)). This will generate errors at synthesis.

Why are you using asynch mode of clearing signals using enable?. Is it on purpose?. Do no use this, this will make your design asynchronous and hence the combo loop.

See, if you want to clear data_count, pre_count use registered enable signal, compare it using clks. You are clearing the registers without clock and then reading the value with many clocks (clk_in, data_sync(1)).

This is no right.

One more suggestion, if you want to detect rising edge, please use a edge detection logic to detect the rising edge, not with the function call "rising_edge". You can do this by using two FFs and and AND gate logic. I recommend not to use this in rising_edge clock function this context.

Use a one-shot pulse logic to generate a pulse with 1 clk width from data_sync(1). Then compare it in your rising_edge(clk_in ) and based on that incr counters...
Like this
Code: 
If rising_edge(clk_in) then
   If enable = '0' then
     data_count <= 0;
     pre_count <= 0;
     pre_count_1 <= 0;
     pre_count_2 <= 0;
   Else   
     if pos_edge_dataSync = '1' then        -- this signal will set if rising_edge is detected at data_sync(0)
        <All Your Count/Clear Logic>
     end if;
   End if;
 

A side remark about reading warnings or error messages.

Besides all code oddities, that have been analyzed by xtcx in detail, it's confusing at first sight, that the tool complains about combinational loops, although the rising_edge() construct seems to demand FFs. To solve the riddle, you need to start reading in the middle of long warnings list. Here you find e.g.:
Code: 
Pruning register data_sync(1 downto 0)  
Input data is unused
In other words, the rising edge trigger has been removed by the compiler, apparently because no design output depends on it. The respective code parts becomes meaningless. The combinational loop warnings are as well, nothing but artefacts of a design tool that vainly tries to make sense of the irrelevant code.
 

the problem is the second process. I suggest making it into a synchrous (rather than a mess) process.
 

FvM said:
A side remark about reading warnings or error messages.

Besides all code oddities, that have been analyzed by xtcx in detail, it's confusing at first sight, that the tool complains about combinational loops, although the rising_edge() construct seems to demand FFs. To solve the riddle, you need to start reading in the middle of long warnings list. Here you find e.g.:
Code: 
Pruning register data_sync(1 downto 0)  
Input data is unused
In other words, the rising edge trigger has been removed by the compiler, apparently because no design output depends on it. The respective code parts becomes meaningless. The combinational loop warnings are as well, nothing but artefacts of a design tool that vainly tries to make sense of the irrelevant code.
Click to expand...

Code: 
@W: MO161 :"c:\users\hqien\desktop\dominick\vhdl tutorial\qrng.vhd":69:8:69:9|Register bit dout is always 1, optimizing ...

I think we need not go too deep, as this clearly says that somewhere the tool has trimmed the logic....so there's going to be no change at the output.

But I wonder why would the tool want to trim the output, I mean is it because the data_sync(1) is never going to change?, why?.
Maybe the rising_edge fn for data_sync() is not taken care by tool
 

But I wonder why would the tool want to trim the output, I mean is it because the data_sync(1) is never going to change?, why?.
Maybe the rising_edge fn for data_sync() is not taken care by tool
Click to expand...
No, it's a well founded analysis result. As you clarified, enable is preventing the first process from increasing pre_count. As a result, all conditions that cause a change in the design output signals are permanently false. trigger and dout are stuck and the design logic can be reduced to nothing.

I only wonder why the tool is complaining about combinational loops of non-existing signals. That's what I see as an artefact.

Consequently, by removing the enable condition, FFs should be inferred for rising_edge(data_sync(1)), making the respective warnings disappear. Possibly other warnings are brought up, but I'm not motivated to further trace this blind alley.
 

    V

    Points: 2
    Helpful Answer Positive Rating
FvM said:
Consequently, by removing the enable condition, FFs should be inferred for rising_edge(data_sync(1)), making the respective warnings disappear. Possibly other warnings are brought up, but I'm not motivated to further trace this blind alley.
Click to expand...

Agreed, but the pre_count is being addressed (Write) at two clocked process as seen by the tool. SO this will throw an error for sure. So if to detect a rising edge, it should be done through an edge detector logic\one shot logic only. Only this can help this guy come out of the problem
 
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    FvM

    FvM

    Points: 2
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