Need help with Clocked comparators testbench

[mavrick2000]

Hi,
I have just completed designing a clocked latched comparator, but I need to characterize it for offset (monte carlo offset histogram), maximum speed, metastability, and sensitivity analysis .... etc. So this is too hard for me as it is clocked, also I looked in many books and nothing on how to do that !! would you please help me

 

[ZekeR]

There's IC design happening in Idaho?

I'd probably be happy doing some DC calcs and waving my hands around saying the transient, clocked sim will match. Then I'd see if the real silicon matched. However, if you insist on doing a real simulation (which, if done right, should take into account many variations that a DC calc wouldn't, such as capacitance mismatches and offset variations over operating point), then I don't presently see any better way than to brute force it. For each iteration, run the input to the comparator as a ramp while clocking it; make sure the clock comes once every, say, 250µV or so. Of course, run the sim slowly enough to ensure transients settle before the comparator gets clocked. Then write a script that goes through the simulation data and picks out when the comparator latched a new state, how long it took, etc. You won't be able to resolve offset better than 250µV in the final data, but when you draw a histogram you dump the data into discrete buckets anyway.

 

[mavrick2000]

Thanks, but can you provide me with any material on how to write a correct calculator expression to get the offset statistical variation histogram. Also if there is a book or tutorial describing the whole process, that would be fine.