Need help: which layout is better?

[patato]

i am working on a 12 bit SARADC(4bit R 8bit C architecture), and get confused on the 4it R_DAC layout plan

fig1-> simply place R1 to R16 from top to bottom, no center-centroid, clear routing
fig2-> center-centroid layout, but the routing is killing me

R1~R16 are 2x20 um2 poly resistor

fig2 would be less suffered by gradient
but the resistance of each routing wires are different,i guess that might be a problem?

so which layout is better?
or there's a even better solution?



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[skas20]

- Figure 2 is the Better layout.
- You need to put dummy resistors on either side of the array for matching the
etching non uniformity.
- If the resistance value is very high, then a small mismatch in the routing
parasitic can be okey. but if the value is less then you need to match the
routing parasitic resistance as well.

Regards,
SK.

 

[manish12]

common centroid must be consider , so second figure is best choice here.

 

[nanrma]

Fig2 is a better placement but u need to add dummy resistors on all 4 sides.