deepu_s_s
Full Member level 5
hi !
These are the questions from exercise of Chapter-7 of Digital Design principles and practices by John .F.Wakerly. plz help me by providing solutions for these questions
1) Explain how metastabiity occurs in D latch when the setup and hold times are not met,analyzing the behaviour of the feedback loop inside the latch
2)what is the minimum setup time of a pulse-triggered flip flop such as a master/slave J-K or S-R flip flop.
3)Describe a situation,other than the metastable state, in which the Q and Qn outputs of a 74x74 edge triggered D flip flop may be non-complementary for an arbotarily long time.
thanks and regards
deepak
These are the questions from exercise of Chapter-7 of Digital Design principles and practices by John .F.Wakerly. plz help me by providing solutions for these questions
1) Explain how metastabiity occurs in D latch when the setup and hold times are not met,analyzing the behaviour of the feedback loop inside the latch
2)what is the minimum setup time of a pulse-triggered flip flop such as a master/slave J-K or S-R flip flop.
3)Describe a situation,other than the metastable state, in which the Q and Qn outputs of a 74x74 edge triggered D flip flop may be non-complementary for an arbotarily long time.
thanks and regards
deepak