navienavnav
Member level 1
The following is the code given for a shift register in my textbook :
I can't understand the statement :
What is this statement doing exactly? I have seen the use of the '=>' operator in CASE but I don't what and how it is doing here.
Please help. :sad:
Code:
ENTITY shiftreg IS
GENERIC (n: INTEGER := 4); -- # of stages
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END shiftreg;
ARCHITECTURE behavior OF shiftreg IS
SIGNAL internal: STD_LOGIC_VECTOR (n-1 DOWNTO 0);
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
internal <= (OTHERS => '0');
ELSIF (clk'EVENT AND clk='1') THEN
internal <= d & internal(internal'LEFT DOWNTO 1);
END IF;
END PROCESS;
q <= internal(0);
END behavior;
I can't understand the statement :
internal <= (OTHERS => '0');
What is this statement doing exactly? I have seen the use of the '=>' operator in CASE but I don't what and how it is doing here.
Please help. :sad: