Need help programming Shift registers in VHDL . .

[bciaren]

Need help generating a preamble using VHDL . .

Hello everyone! Could someone help me pick out the flaws in my design? I'm trying to create a preamble using shift registers, but I'm having trouble putting it together..

Here's a picture of the shift registers I'm trying to emulate. .. .


Only rather then the 3 registers, I have 8 to make a byte.
I'm using an XOR gate as an input.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SFD is
  port(clk              :in   std_ulogic;
       resetb          :in   std_ulogic;
       decode_SFD_out   :out std_ulogic);
   end SFD;
   
   architecture preamble of SFD is
     signal shiftreg_8    :std_ulogic_vector(7 downto 0);
     signal F                       :std_ulogic;
     signal A                       :std_ulogic;
     signal B                       :std_ulogic;
   begin
          
     process(shiftreg_8, resetb) is
       begin
         if (resetb = '1') then
         shiftreg_8 <=(others => '0');
       elsif rising_edge(clk) then
         shiftreg_8(0) <= F;
         shiftreg_8(1) <= shiftreg_8(0) then A <= shiftreg_8(1);
         shiftreg_8(2) <= shiftreg_8(1);
         shiftreg_8(3) <= shiftreg_8(2);
         shiftreg_8(4) <= shiftreg_8(3);
         shiftreg_8(5) <= shiftreg_8(4);
         shiftreg_8(6) <= shiftreg_8(5);
         shiftreg_8(7) <= shiftreg_8(6) then B <= shiftreg)8(7);
       end if;
     end process;
     
     Process(shiftreg_8)
       begin
         if(shiftreg_8 ="10101011") then
         decode_SFD_out <='1'
       else
         decode_SFD_out <= '0';
       end if;
     end process;
     F := A XOR B;
    
   end preamble;

I'm a noobie as you can see, and any assistance is appreciated

 

[Mwnuk]

so I am no expert but you can do something simplier than all that, but first let me just say that using a switch as an undedicated clock (as in my example) is in general a bad idea. Having said that, this works.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity shiftreg is
    Port ( LEDs : out  STD_LOGIC_VECTOR(7 downto 0);
			  clk : in  STD_LOGIC;
           switch : in  STD_LOGIC
			 );
end shiftreg;

architecture Behavioral of shiftreg is
signal shiftreg : STD_LOGIC_VECTOR(7 downto 0) := "01010101";

begin

process(switch)
begin
	if rising_edge(switch) then
		shiftreg <= "0"&shiftreg(7 downto 1);
	end if;
end process;




LEDs <= shiftreg;

end Behavioral;

 

[bciaren]

I'd like to implement counters, but I'm not sure how to.. Thanks for e response though! I'll try it when I get home.

 

[TrickyDicky]

plenty of syntax errors -I suggest reading a VHDL tutorial.

Hints - "then" can only be used as part of an if.
:= is used to assign variables, not signals.

 

[Mwnuk]

where is "then" being used not in an if?

like I said I am no expert, but the code does work as intended.

 

[TrickyDicky]

where is "then" being used not in an if?
like I said I am no expert, but the code does work as intended.

In the origional code:
shiftreg_8(1) <= shiftreg_8(0) then A <= shiftreg_8(1);

for example

 

[FvM]

the code does work as intended.

There are least 5 syntax errors that won't be accepted by any VHDL compiler or simulator I know.

You did not compile the code shown in post 1.

where is "then" being used not in an if?

Did you see the "then" syntax in any VHDL text book, tutorial or example code?

 

[Mwnuk]

In the origional code:
shiftreg_8(1) <= shiftreg_8(0) then A <= shiftreg_8(1);

for example

my mistake i did not see that. I just hate it when experienced people tell inexperienced people to go read a book. They are reading books, if they were not they wouldnt have had a question to begin with. What they lack is the years of experience and training that you have.

when someone says go read a book or tutorial I think, why did you bother posting anything because that was not helpful.

 

[TrickyDicky]

Syntax errors are usually fixed simply - the errors are usually pointed out by the compiler and the user should be referencing back to a VHDL tutorial/reference book on the VHDL syntax. Basically, syntax errors usually dont need a post on this forum. So the OP was clearly not running his code through a compiler or referencing his VHDL tutorial.

 

[FvM]

I just hate it when experienced people tell inexperienced people to go read a book.

Did I say this? I was just asking where you got the syntax from.

Posting code that you never compiled and claim it does work means somehow fooling other forum members, isn't it?

 

[Mwnuk]

Did I say this? I was just asking where you got the syntax from.

sort of two conversations going on here, this was referring to the following:

plenty of syntax errors -I suggest reading a VHDL tutorial.

which was addressed by TrickyDicky who originally wrote it.

Posting code that you never compiled and claim it does work means somehow fooling other forum members, isn't it?

My code does compile and runs just fine.

 

[FvM]

My code does compile and runs just fine.

I have two explanations:
- you did not actually compile the code posted in post #1 but something similar
- you are using a very strange VHDL compiler that compiles code with serious syntax errors

I guess, it's the first case.

 

[Mwnuk]

you did not actually compile the code posted in post #1 but something similar

The code from post 1 is not my code.

Posting code that you never compiled and claim it does work means somehow fooling other forum members, isn't it?

my code is post #2, which compiles and works as intended

 

[bciaren]

Thank you for the comments and I apologize for my negligence. Here's the code compiled error free.. Now I need to move on to the next step, but after reviewing my picture I think I understand that this code actually won't work. In order for this to function I need to force a 1, but I don't wish to force a one each time. How can I generate randomness to the shift registers? What I wrote was my initial attempt. .

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SFD is
  port(clk              :out   std_ulogic;
       resetb           :out   std_ulogic;
       data_in          :out   std_ulogic;
       decode_SFD_out   :out std_ulogic);
   end SFD;
   
   architecture preamble of SFD is
      signal clock               : std_ulogic:='0';
      signal shiftreg_8          : std_ulogic_vector(7 downto 0);
      signal decode_SFD          : std_ulogic;
      signal reset_f             : std_ulogic :='0';
      signal F                   : std_ulogic;
      signal A                   : std_ulogic;
      signal B                   : std_ulogic;
      signal counter_A           : std_ulogic;
      signal counter_B           : std_ulogic;       
   begin
     process(reset_f, counter_A, clock) is
      begin
      if (reset_f = '1') then
        counter_A <= '0';
        elsif (clock'event and clock = '1') then
        counter_A <= '1';
      else
        counter_A <= '0';
      end if;
      
      A <= counter_A;
    end process;
    
     process(reset_f, counter_B, clock) is
      begin
      if (reset_f = '1') then
        counter_B <= '0';
        elsif (clock'event and clock = '1') then
        counter_B <= '0';
      else
        counter_B <= '1';
      end if;
      B <= counter_B;
    end process;
           
     process(shiftreg_8, reset_f) is
       begin
         if (reset_f = '1') then
         shiftreg_8 <=(others => '0');
       elsif rising_edge(clock) then
         shiftreg_8(0) <= F;
         shiftreg_8(1) <= shiftreg_8(0);
         shiftreg_8(2) <= shiftreg_8(1);
         shiftreg_8(3) <= shiftreg_8(2);
         shiftreg_8(4) <= shiftreg_8(3);
         shiftreg_8(5) <= shiftreg_8(4);
         shiftreg_8(6) <= shiftreg_8(5);
         shiftreg_8(7) <= shiftreg_8(6); 
       
     
   end if;
     end process;
     
     Process(shiftreg_8)
       begin
         if(shiftreg_8(7 downto 0) ="10101011") then
         decode_SFD <= '1';
       else
         decode_SFD <= '0';
       end if;
     end process;
     F <= A XOR B;
     decode_SFD_out <= decode_SFD;
   end preamble;

Is my logic correct here? I also just realized that my XOR gate will always be popping out a 1 because its inputs will always be 10 01 10 01 10 01 lol :-?

 

[bciaren]

Thank you for the help