I am making a residue amplifier for pipelined ADC on 65 nm node
Can any one tell me detailed working of switched CMFB
What will happen if there is an offset in the bias voltage set by the replica and actual bias voltage required?
Is there any way to ensure zero offset across all process cornets and temperatures?
Hi,
I don't tink it would be zero in all corners, but you can decrease it adequately. This paper includes a good research on CMFB:
"Analysis of Switched-Capacitor Common-Mode Feedback Circuit",
By: Ojas Choksi and L. Richard Carley,
TCAS II, 2003.