Need help on hot carrier stress test using TCAD Silvaco Atlas

[sweetmicroe]

Good day to all here..

I like to seem some advice and help from experts here regarding my project.

Basically, as we all know the hot channel effect (HCE) can be reduced by using lightly doped drain (LDD) structure. My project is to further study on the hot carrier effect on LDD NMOS structure - want to study how much further degradation happen with LDD structure and what process parameter that could help to reduce in further.

I am doing this study on 90nm NMOSFET. Based on the structure that I have done, it gives threshold voltage of 0.25V at drain bias=0.2V.

Now, I am doing stress test for 50s up to 1000s. But it seems like the threshold voltage is shifted in huge value to 2-3V. As I know, the stress would shift the threshold voltage about mV. When I set it to stress at only 10s, its already shifted to ~0.8V. This is where my work is stucked and I cannot proceed.

Therefore I would like to seek some help from expert here:

1. Why is the threshold voltage shift too large? I have tried many times and none doesn't tally with the journal paper I have been studied.
2. I am looking for a script to plot the transconductance, gm vs Vgs. Does anyone can help me here?
3. To study on the HCE, I would need to look at the degradation of the Vth, Id and gm. Is there anything else do I need to look for?

By the way, I am using Silvaco Atlas for the characterization.

Hope to get the answer soon. Thanks. :smile:

 

[timof]

While simulation of carrier transport in semiconductor devices is more or less "first principle", simulation of degradation is not.
That is true for any type of degradation - HCE (Hot Carrier Effect), NBTI (Negative Bias Temperature Instability), TDDB (Time-Dependent Dielectric Breakdown), etc.
There are not first-principle models predicting the degradation dynamics (or statics) more or less "predictively".
Degradation is strongly affected by obscure process, chemical, and other effects that are far from being well understood or described by any theory - nitridation of gate oxides, hydrogenation or deuteriazation of the interface defects/traps, presence of fluorine or other chemicals, etc. etc.

It appears that there are some empirical models in device simulation tools (including Silvaco's Atlas) that do allow to simulate some degradation effects.
If so, there should be some tuning or fitting parameters, that you can change in the input deck, to tune your simulation results.
Then you will get few mV or few tens of mV of degradation after X hours of "stress", instead of unreasonable few Volts.

Hopefully, those empirical models account for the effect of the electric field ion the hot carrier degradation, so that when you change LDD doping profile, you will see the change of electric field and then, hopefully, change in degradation.

In the past, an indirect indication of the strength of hot carrier effect was substrate current (also generated by hot carriers).
People observed, experimentally, a correlation between the degradation and the peak substrate current (vs gate voltage, at max Vds).
So, the magnitude of the substrate current was used as a "proxy" for degradation.

 

[dick_freebird]

Oxide qualities determine how much of the carriers thrown,
are trapped vs drifted out, and how often they create a
new trap or depassivate an existing one. Unless you are
taking advantage of a recipe that someone has already fitted,
those qualitative things (represented by some quantitative
params no doubt) are a wild guess.

The carrier flux vs junction field and how they are steered by
oxide fields, is probably less "squishy". But getting gate ox
and spacers to be decently reliable, gets a lot of engineering
beyond just LDD doping and extent in process developments.

 

[sweetmicroe]

Thanks for the replies.

I don't have fitted recipe for the device that I am doing. My lecturer was asking me to look from journal or conference paper that people produced and take those number such as doping profile, size and etc to build my own 90nm structure. I have been searching from IEEE, IOP Science, Science Direct but it is very hard to get the whole process parameter from 1 single paper. So, I have mixed from multiple reference paper for the device. Also, my lecturer did not allow me to just pick any number of profile which does not has valid reference. So, by mixing them up, I believe it is hard to replicate the result shown by the papers.

So, due to that, I have to make my own 90nm LDD structure based on few reference: I have to mix and match few process parameter such as doping profile for substrate, n+, n-, vth ion implant etc. Also, I have to meet the correct threshold voltage by comparing to theoretical calculation. So, I have done is I did my calculation to get the desired Vth value (in my case is 0.24V with substrate doping profile is 7.51e17). From there I done some tuning on other parameter such as channel doping concentration, spacer size, oxide thickness etc to meet the simulated Vth close to 0.24V. I am not sure whether this is the correct way to construct a mosfet structure?

Maybe I need some little help, if you guys have any valid reference of 90nm LDD NMOS structure that I could duplicate for my study?

 

[sweetmicroe]

Btw, the stressing test script that i am using is from example mos2ex02.in from Silvaco in below link. The code is stressing from 0.01s to 1000s. Seems like I got the similar trend of shifted Vth. I am not sure whether the code is correct in stressing the device? Does the stressing time of 0.01s valid? I think it is too short in stressing the device and huge vth different between non-stress and 0.1s.

https://www.silvaco.com/examples/tcad/section36/example2/index.html

Does anybody here expert in silvaco can give me the code for only to stress the device? Let say, I want to stress the device at particular Vg, Vd, temperature and time. I believe this are the stressing condition that I am concerning. If any of you guys have the code, could you share with me so I can compare the result with the code from Silvaco example?

Thanks.