Need Help in VHDL Down-Converter

[YenYu]

Hi Everyone, currently i'm doing a final year project. I'm having a problem on the output signal. My It2 doesnt seems to haf clk, it's just gif an output of 0(decimal) all the way. Not like Xr2 or Xi2. The following is my Main program and test bench.
The filter is generated from GEN Core. It's a DA FIR 32 tap filter. I dont know where went wrong. Thx and i really need some help.

Main Program
-----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity DownConverter is
Port ( g_clk,res : in STD_LOGIC;
X : in STD_LOGIC_VECTOR(9 downto 0);
Xr2: out STD_LOGIC_VECTOR(9 downto 0);
Xi2 : out STD_LOGIC_VECTOR(9 downto 0);
It2 : out STD_LOGIC_VECTOR(26 downto 0)
);
end DownConverter;

architecture main OF DownConverter is
type state is (Start,S1,S2,S3,S4);
Signal Current_state,Next_state : State;
Signal Xr2i,Xi2i : STD_LOGIC_VECTOR(9 downto 0);
Signal sclr : STD_LOGIC;
Signal rfd,rdy : STD_LOGIC;
Signal nd : STD_LOGIC;
Signal dout : STD_LOGIC_VECTOR(26 downto 0);
Signal din : STD_LOGIC_VECTOR(9 downto 0);
-------------------------------------------------------------
-- Declare Component <Filter>
Component filter is
port (
sclr : in STD_LOGIC:='1';
rfd : out STD_LOGIC;
rdy : out STD_LOGIC;
nd : in STD_LOGIC := '1';
clk : in STD_LOGIC := '1';
dout : out STD_LOGIC_VECTOR ( 26 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end Component;
begin
--Component Instantiation
u2:component Filter Port Map (din=>din,
dout=>dout,
clk=>g_clk,
sclr=>res,
rfd=>rfd,
rdy=>rdy,
nd=>nd
);
-------------------------------------------------------------
process ( g_clk,res )
begin
if res='1' then
Current_state <= Start;
elsif (g_clk'event and g_clk='1') then
Current_state <= Next_state;
end if;
end process;

process ( Current_state,X )
begin

case Current_state is
when Start=> Next_state <= S1;
Xr2i<= X ; Xi2i<= "0000000000" ;
when S1 => Next_state <= S2;
Xr2i<= "0000000000" ; Xi2i<= 0-X;
when S2 => Next_state <= S3;
Xr2i<= 0-X ; Xi2i<= "0000000000" ;
when S3 => Next_state <= S4;
Xr2i<= "0000000000" ; Xi2i<= X ;
when S4 => Next_State <= S1;
Xr2i<= X ; Xi2i<= "0000000000" ;

end case;
end process;
nd<= '1';
sclr<=res;
Xr2<=Xr2i;
Xi2<=Xi2i;
Din<=Xr2i;
It2<=Dout;
end;
-----------
Test Bench
-------------------
LIBRARY ieee;
USE ieee.std_logic_textio.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;

-- Entity
ENTITY DownTB IS
END;

ARCHITECTURE TB OF DownTB IS

-- Component Declaration
COMPONENT DownConverter
PORT(
g_clk: IN std_logic; -- Clock
res : IN std_logic; -- Reset
X : IN std_logic_vector(9 downto 0); -- Input
It2 : OUT STD_LOGIC_VECTOR(26 downto 0); -- Output
Xr2 : OUT std_logic_vector(9 downto 0);
Xi2 : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;

For u1: DownConverter use entity work.DownConverter(Main);

SIGNAL g_clk : std_logic:='1';
SIGNAL res : std_logic:='1';
SIGNAL X : std_logic_vector(9 downto 0);
SIGNAL Xr2,Xi2 : std_logic_vector(9 downto 0);
SIGNAL It2 : std_logic_vector(26 downto 0);

BEGIN

-- Component Instantiation
u1: DownConverter PORT MAP(g_clk=>g_clk,
res=>res,
X=>X,
Xr2=>Xr2,
Xi2=>Xi2,
It2=>It2);

res <= '1','0' after 50 ns;
g_clk <= not g_clk after 75 ns;


---------- READ AND WRITE FILE ------------
----READ FROM FILE----
PROCESS
File x_b : text IS "./x_b.txt";
Variable txtline : line;
Variable X_buff : std_logic_vector ( 9 downto 0 );

Begin
While not endfile ( x_b ) LOOP

readline (x_b,txtline);
read (txtline,x_buff);

x<=x_buff;
wait for 150 ns;
end loop;
wait;
end process;
end;