[SOLVED] need help in modelsim se vhdl intermediate signals

[chaitanya.531]

hi

i am new with vhdl and model sim ;

i want to view intermediate signals in my entity ;
simulator used is modelsim ;

plz help me

 

[imbichie]

Hi, If you wants to see all the signals just type the command in the trnscript window


#==== run the simulation
vsim -novopt -t 1ps test_bench_name

add wave -r /*



The above command will simulate your design without neglecting the signals and also adds all the signals in your design...

Take care to replace the test_bench_name as your test_bench's name...

hope it will help...

 

[chaitanya.531]

it worked
but i want to view internal signal at every time
is there any testbench modification for view internal signals as the output wavesss...
plz

 

[imbichie]

Hi,

Using this command
add wave -r /*
you can see all the signals both in the rtl and in the testbench in your modelsim's wave window...?

Then about which signal you are talking?

---------- Post added at 16:27 ---------- Previous post was at 16:27 ----------

In this case all the signals are your output wave na...?

 

[chaitanya.531]

the signals that varies with time
variables
it shows the end results not the wave forms

as shown in figure

i want the signals at every time on scale

 

[imbichie]

when you use this command
add wave -r /*

The command should be used before the run started...

Means the things will be like this..

Compile the files
simulate the testbench
add the waves (Here you can use the command)

run the simulation...

Is your Procedure like this..?

---------- Post added at 16:53 ---------- Previous post was at 16:50 ----------

This is an example of the ModelSim's TCL Script

means the filename.do file in the ModelSim

The command is like this

do filename.do


The content of the filename.do file is like this

if {!0} {
    vlib work 
}

vmap work work


#==== compile

vcom \
	real_pkg.vhd \
	real_std_logic_vector.vhd \
	counter.vhd \
	real_std_logic_vector_tb.vhd
	
#==== run the simulation
vsim  -novopt -t 1ps real_std_logic_vector_tb  
if {[catch [set StdArithNoWarnings 1] temp ]} {}
if {[catch [set NumericStdNoWarnings 1] temp ]} {}
if {[catch [set IgnoreWarning 1] temp ]} {}
add wave -r -radix hex /*
run 500 us

 

[chaitanya.531]

ya i made wrong

i get it