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need help in folded cascode design

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Member level 3
Jan 27, 2006
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Can anyone send me design equations of folded cascode ota using settling time constraint.
I tried with slew rate limit,but I am unable to get the desired settling time.

just send me design equations of NMOS input fully differential
folded cascode opamp.

you can look for the handout of EE240(Boser, Berkley)

The document is quite informative. But I have doubt,why should we use 1:4 it compulsory,as I have read,if we want an OTA,use equal currents. Please clarify to me.

The 1:4 ratio of the input to cascode current is not compulsory. Many text books state this as a means of maximizing gain. It is true, gain is improved due to higher output resistance.

However it is more common in my experience to decrease the ratio to a more realistic and robust level like 1:2. The reason is that in practical applications, device mismatch can exceed 25%, particularly in CMOS foundry technologies. If you use 1:4 ratio in this case, the cascode transistor can be biased at ZERO current! You've fallen off the cliff edge. In the real world of manufacturable designs, we want to stay as far away from cliff edges as possible.

jgarciarivera said:
Here is a file with some tips on folded cascode design.

Very good material,thank you very much!!!

actually linear settling time of opamp depends upon the UGB of the opamp.
total settling time=slewing time+linear settling time.
now if you are not able to meet the settling time spec inspite of meeting the slew rate spec,try to increase the bandwidth of the opamp.this will reduce the linear settling to increase the bandwidth you have to increase the gm of the differential input-pair just increase the size of these transistors,you might get the reduced settling time.

**broken link removed**

jgarciarivera said:
Here is a file with some tips on folded cascode design.
The pdf file is wonderful. Would you like to share the whole of this pdf file? Thanks.

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