I'm trying to implement a simple RAM (for the SP601 evaluation kit) that will store a 12-bit data. I've seen many sample codes from XST user guide such as this one
libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity RAM_src isPORT(CLK :instd_logic;
en :instd_logic;
we :instd_logic;
addr :instd_logic_vector(5downto0);
d_in :instd_logic_vector(11downto0);
d_out :outstd_logic_vector(11downto0));end RAM_src;architecture Behavioral of RAM_src istype ram_type isarray(63downto0)ofstd_logic_vector(11downto0);signal RAM : ram_type;signal read_a :std_logic_vector(5downto0);begin
d_out <= RAM(conv_integer(read_a));
memory:process(CLK)beginif rising_edge (CLK)thenif en = '1' then-- enableif we = '1' then-- write enable
RAM(conv_integer(addr))<= d_in;
read_a <= addr;endif;endif;endif;endprocess memory;end Behavioral;
From that code, is it possible that an input is stored/written in a selected/defined address so that I only have to access that address if I want to read that data?
Also, does anyone know how to test that RAM code (with testbench, maybe)?
libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity RAM_src isPORT(CLK :instd_logic;
en :instd_logic;-- global enable
we :instd_logic;-- write enable
addr :instd_logic_vector(8downto0);-- adress bit vector
d_in :instd_logic_vector(11downto0);
d_out :outstd_logic_vector(11downto0));end RAM_src;architecture Behavioral of RAM_src istype ram_type isarray(511downto0)ofstd_logic_vector(11downto0);--512 locations in RAMsignal RAM : ram_type;begin
memory :process(CLK)beginif rising_edge (CLK)thenif en = '1' thenif we = '1' then
RAM(conv_integer(addr))<= d_in;-- readendif;
d_out <= RAM(conv_integer(addr));-- writeendif;endif;endprocess memory;end Behavioral;
so is there any way to select the address to store input only to that address?